ADRF6620ACPZ-R7 datasheet(10/52 Pages) AD

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ADRF6620

Data Sheet

Rev. 0 | Page 10 of 52

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC1

DECL1

GND

REFIN

DECL2

IFOUT1+

IFOUT1–

IFOUT2+

IFOUT2–

VCC2

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND

PLANE WITH LOW THERMAL IMPEDANCE.

RFIN0

GND

RFIN1

GND

RFIN2

GND

RFIN3

GND

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

ADRF6620

Figure 3. Pin Configuration

Table 9. Pin Function Descriptions1

Pin No.

Mnemonic

Description

1, 12, 13, 14, 24

VCC1, VCC2, VCC3,

VCC4, VCC5

5 V Power Supplies. Decouple all power supply pins to ground, using 100 pF and 0.1 µF

capacitors. Place the decoupling capacitors near the pins.

2, 7, 37, 46

DECL1, DECL2,

DECL3, DECL4

Decouple all DECLx pins to ground, using 100 pF, 0.1 µF, and 10 µF capacitors. Place the

decoupling capacitors near the pins.

Synthesizer Charge Pump Output. Connect this pin to the VTUNE pin through the loop filter.

4, 5, 17, 20, 23, 25, 27,

28, 30, 31, 33, 34, 36, 48

GND

Ground.

REFIN

Synthesizer Reference Frequency Input.

8 to 11

IFOUT1+, IFOUT1−,

IFOUT2+, IFOUT2−

IF DGA Outputs. Connect the positive pins such that IFOUT1+ and IFOUT2+ are tied

together. Similarly, connect the negative pins such that IFOUT1− and IFOUT2− are tied

together. Refer to the Layout section for a recommended layout that minimizes parasitic

capacitance and optimizes performance.

15, 16

IFIN−, IFIN+

Differential IF DGA Inputs. AC couple the mixer outputs to the IF DGA inputs.

18, 19

MXOUT+, MXOUT−

Differential Mixer Outputs. AC couple the mixer outputs to the IF DGA inputs.

21, 22

LOOUT+, LOOUT−

Differential LO Outputs. The differential output impedance is 50 Ω.

26, 29, 32, 35

RFIN3, RFIN2,

RFIN1, RFIN0

RF Inputs. These single-ended RF inputs have a 50 Ω input impedance and must be

ac-coupled.

38, 39

RFSW0, RFSW1

External Pin Control of RF Input Switches. For logic high, connect these pins to 2.5 V logic.

SPI Chip Select, Active Low. 3.3 V tolerant logic levels.

SCLK

SPI Clock. 3.3 V tolerant logic levels.

SDIO

SPI Data Input or Output. 3.3 V tolerant logic levels.

MUXOUT

Multiplexer Output. This output pin provides the PLL reference signal or the PLL lock

detect signal.

44, 45

LOIN−, LOIN+

Differential Local Oscillator Inputs. The differential input impedance is 50 Ω.

VTUNE

VCO Tuning Voltage. Connect this pin to the CP pin through the loop filter.

EPAD

Exposed Pad. The exposed pad must be connected to a ground plane with low thermal

impedance.

For more connection information about these pins, see Table 14.

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