ADRF6620ACPZ-R7 datasheet(25/52 Pages) AD

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Data Sheet

ADRF6620

Rev. 0 | Page 25 of 52

TUNABLE BALUN

The ADRF6620 integrates a programmable balun operating over

a frequency range from 700 MHz to 2700 MHz. The tunable

balun offers the benefit of ease of drivability from a single-ended

50 Ω RF input, and the single-ended-to-differential conversion

of the balun optimizes common-mode rejection.

BAL_COUT

REG 0x30[7:5]

BAL_CIN

REG 0x30[3:1]

RFINx

Figure 67. Integrated Tunable Balun

The RF balun is tuned by switching parallel capacitances on the

primary and secondary sides by writing to Register 0x30. The

added capacitance, in parallel with the inductive windings of the

balun, changes the resonant frequency of the inductive capacitive

(LC) tank. Therefore, selecting the proper combination of BAL_

CIN (Register 0x30, Bits[3:1]) and BAL_COUT (Register 0x30,

Bits[7:5]) sets the desired frequency and minimizes the insertion

loss of the balun. Under most circumstances, the input and output

can be tuned together; however, sometimes for matching reasons,

it may be advantageous to tune them separately. See the RF Input

Balun Insertion Loss Optimization section for the recommended

BAL_CIN and BAL_COUT settings.

RF DIGITAL STEP ATTENUATOR (DSA)

The RF DSA follows the tunable balun. The attenuation range is

0 dB to 15 dB with a step size of 1 dB. DSA attenuation is set using

the RFDSA_SEL bits (Register 0x23, Bits[8:5]).

ACTIVE MIXER

The double balanced mixer uses high performance SiGe NPN

transistors. This mixer is based on the Gilbert cell design of four

cross-connected transistors.

The mixer output has a 255 Ω differential output resistance.

Bias the mixer outputs using either a pair of supply referenced

RF chokes or an output transformer with the center tap connected

to the positive supply.

DIGITALLY PROGRAMMABLE VARIABLE GAIN

AMPLIFIER (DGA)

The ADRF6620 integrates a differential IF DGA consisting of a

150 Ω digitally controlled passive attenuator followed by a highly

linear transconductance amplifier with feedback. The attenuation

range is 12 dB, and the transconductor amplifier has a fixed gain

of 15 dB. Therefore, at minimum attenuation, the gain of the IF

DGA is 15 dB; at maximum attenuation, the gain is 3 dB. The

attenuation is controlled by addressing the IF_ATTN bits in

REF

IFIN+

IFIN–

IFOUT1+

IFOUT1–

IFOUT2+

IFOUT2–

ATTENUATOR

RIN

OUT

+5V

AMP

LOGIC

Figure 68. Simplified IF DGA Schematic

An independent internal voltage reference circuit sets the dc

voltage level at the input of the amplifier to approximately 1.5 V.

This reference is not accessible and cannot be adjusted.

The IF DGA consumes 35 mA through the VCC2 pin (Pin 12)

and 75 mA through the two output choke inductors. The IF

DGA can be powered down by disabling the IF_AMP_EN bit

(Register 0x01, Bit 11). In its power-down state, the IF DGA

current reduces to 6 mA. The dc bias level at the input remains

at approximately 1.5 V when the DGA is disabled.

At minimum attenuation, the gain of the IF DGA is 15 dB when

driving a 150 Ω load. The source and load resistance of the

amplifier is set to 150 Ω in a matched condition. If the load or

the source resistance is not equal to 150 Ω, the following equations

can be used to determine the resulting gain and input/output

resistances.

Voltage Gain = AV = 0.044 × (1000||RL)

RIN = (1000 + RL)/(1 + 0.044 × RL)

S21 (Gain) = 2 × RIN/(RIN + RS) × AV

ROUT = (1000 + RS)/(1 + 0.044 × RS)

The dc current to the outputs of each amplifier is supplied

through two external choke inductors. The inductance of the

chokes and the resistance of the load, in parallel with the output

resistance of the device, add a low frequency pole to the response.

The parasitic capacitance of the chokes adds to the output capa-

citance of the part. This total capacitance, in parallel with the

load and output resistance, sets the high frequency pole of the

device. In general, the larger the inductance of the choke, the

higher the parasitic capacitance. Therefore, this trade-off must be

considered when the value and type of the choke are selected.

For each polarity, the amplifier has two output pins that are

oriented in an alternating fashion: IFOUT1+ (Pin 8), IFOUT1−

(Pin 9), IFOUT2+ (Pin 10), and IFOUT2− (Pin 11). When

designing the board, minimize the parasitic capacitance caused

by routing the corresponding outputs together. See the Layout

section for the recommended printed circuit board (PCB)

layout.

ADRF6620ACPZ-R7 Datasheet(PDF) 25 Page - Analog Devices

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