ADRF6620ACPZ-R7 datasheet(40/52 Pages) AD

40 / 52 page

ADRF6620

Data Sheet

Rev. 0 | Page 40 of 52

POWER MODES

The ADRF6620 has many building blocks, and these blocks can

be independently powered off by writing to Register 0x01 (see

Table 23).

External LO Mode

In external LO mode, the internal PLL and VCO are disabled,

which reduces the current consumption by approximately 100 mA.

Table 20 lists the register settings that are required to configure

external LO mode.

Table 20. Serial Port Configuration for External LO Mode

Bit Name

State

LDO_3P3_EN

0x01 = 0x8B53

VCO_LDO_EN

0x01 = 0x8B53

CP_EN

Off

0x01 = 0x8B53

DIV_EN

Off

0x01 = 0x8B53

VCO_EN

0x01 = 0x8B53

REF_BUF_EN

Off

0x01 = 0x8B53

LO_DRV_EN

Off

0x01 = 0x8B53

LO_PATH_EN

0x01 = 0x8B53

MIX_EN

0x01 = 0x8B53

IF_AMP_EN

0x01 = 0x8B53

LO_LDO_EN

0x01 = 0x8B53

VCO_SEL

External LO

0x22, Bits[2:0] = 011

IF DGA Disable Mode

In applications where the IF DGA is not used, it can be powered

down. Power-down is achieved by disabling the IF_AMP_EN bit

(Register 0x01, Bit 11 = 0). By disabling the amplifier, the current

consumption of the ADRF6620 decreases by approximately 25 mA,

along with a 35 mA to 50 mA current savings through each bias

inductor at the output of the amplifier. When the IF DGA is

disabled, its input and output impedance is high-Z. For this reason,

the input and output pins can be left open. If the preference is

not to leave the nodes open, the alternative option is to terminate

the pins to ground via a 1 kΩ resistor.

LAYOUT

Careful layout of the ADRF6620 is necessary for optimizing

performance and minimizing stray parasitics. Because the

ADRF6620 supports four RF inputs, the layout of the RF section

is critical in achieving isolation between each channel. Figure 100

shows the recommended layout for the RF inputs. Each RF input,

RFIN0 to RFIN3, is isolated between ground pins, and the best

layout approach is to keep the traces short and direct. To achieve

this layout, connect the pins directly to the center ground pad

of the exposed pad of the ADRF6620. This approach minimizes

the trace inductance and promotes better isolation between the

channels. In additional, for improved isolation, do not route the

RFIN0 to RFIN3 traces in parallel to each other; instead, spread

the traces immediately after each one leaves the pins. Keep the

traces as far away from each other as possible (and at an angle,

if possible) to prevent cross coupling.

The input impedance of the RF inputs is 50 Ω, and the traces

leading to the pin must also have a 50 Ω characteristic impedance.

Terminate unused RF inputs with a dc blocking capacitor to

ground.

RFIN 0

RFIN 1

RFIN 2

RFIN 3

GND

Figure 100. Recommended Layout for the RF Inputs

The IF DGA outputs on the ADRF6620 have two output pins for

each polarity, and they are oriented in an alternating fashion, as

follows: IFOUT1+ (Pin 8), IFOUT1− (Pin 9), IFOUT2+ (Pin 10),

and IFOUT2− (Pin 11). When designing the board, minimize the

parasitic capacitance due to the routing that connects the corre-

sponding outputs together. A good practice is to avoid any ground

or power plane under this routing region and under the chokes

to minimize the parasitic capacitance. Figure 101 shows the

recommended layout. The IF DGA output pins with the same

polarity are tied together on the bottom of the board with the

blue traces and vias.

IFOUT1+

IFOUT1–

IFOUT2+

IFOUT2–

Figure 101. Recommended Layout for the IF DGA Outputs

(Green traces are routings on top of the board,

and blue traces are routings on the bottom of the board.)

ADRF6620ACPZ-R7 Datasheet(PDF) 40 Page - Analog Devices

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