ADRF6620ACPZ-R7 datasheet(29/52 Pages) AD

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Data Sheet

ADRF6620

Rev. 0 | Page 29 of 52

Pin No.

Mnemonic

Description

Basic Connection

are internally biased to 2.5 V and must be ac-coupled.

44, 45

LOIN−, LOIN+

Differential LO inputs

The differential input impedance of these pins is 50 Ω. The pins

are internally biased to 2.5 V and must be ac-coupled.

MUXOUT

PLL multiplex output

This output pin provides the PLL reference signal or the PLL lock

detect signal.

VTUNE

VCO tuning voltage

This pin is driven by the output of the loop filter; its nominal

input voltage range is 1.5 V to 2.5 V.

RF Inputs

26, 29, 32, 35

RFIN3, RFIN2

RFIN1, RFIN0

RF inputs

The single-ended RF inputs have a 50 Ω input impedance and

are internally biased to 2.5 V. These pins must be ac-coupled.

Terminate unused RF inputs with a dc blocking capacitor to

GND to improve isolation. Refer to the Layout section for the

recommended PCB layout for optimized channel-to-channel

isolation.

38, 39

RFSW0, RFSW1

Pin control of the RF inputs

See Table 10 for the pin settings for RF input pin control. For

logic high, connect these pins to 2.5 V logic.

IF DGA

8, 9, 10, 11

IFOUT1+, IFOUT1−,

IFOUT2+, IFOUT2−

IF DGA outputs

The differential IF DGA outputs have two output pins for each

polarity. They are oriented in alternating fashion: IFOUT1+ (Pin 8),

IFOUT1− (Pin 9), IFOUT2+ (Pin 10), and IFOUT2− (Pin 11).

Connect the positive pins such that IFOUT1+ and IFOUT2+ are

tied together. Similarly, connect the negative pins such that

IFOUT1− and IFOUT2− are tied together. Refer to the Layout

section for a recommended layout that minimizes parasitic

capacitance and optimizes on performance.

The output stage of the IF DAG is an open-collector configuration

that requires a dc bias of 5 V. Use bias choke inductors to

achieve this configuration. Choose the bias choke inductors

such that they can handle a maximum current of 50 mA on

each side. By design, the IF DGA is optimized for linearity when

the source and load are terminated with 150 Ω.

15, 16

IFIN−, IFIN+

IF DGA inputs

AC couple the mixer outputs to the IF DGA inputs. See the

Interstage Filtering Requirements section for the recommended

filter designs.

Mixer Outputs

18, 19

MXOUT+, MXOUT−

Differential mixer outputs

The output stage of the mixer is an open collector configuration

that requires a dc bias of 5 V. Use bias choke inductors to achieve

this configuration. Carefully choose the bias choke inductors

such that they can handle a maximum current of 50 mA on each

side. The differential output impedance of the mixer is 255 Ω.

Serial Port Interface

SPI chip select

Active low. 3.3 V logic levels.

SCLK

SPI clock

3.3 V tolerant logic levels.

SDIO

SPI data input and output

3.3 V tolerant logic levels.

LDO Decoupling

DECL1

3.3 V LDO decoupling

Decouple all DECLx pins to ground using 100 pF, 0.1 µF, and 10 µF

capacitors. Place the decoupling capacitors close to the pin.

DECL2

2.5 V LDO decoupling

DECL3

LO LDO decoupling

DECL4

VCO LDO decoupling

GND

4, 5, 17, 20, 23, 25,

27, 28, 30, 31, 33,

34, 36, 48

GND

Ground

Connect these pins to the GND of the PCB.

49 (EPAD)

Exposed pad (EPAD)

The exposed thermal pad is on the bottom of the package.

The exposed pad must be soldered to ground.

ADRF6620ACPZ-R7 Datasheet(PDF) 29 Page - Analog Devices

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