ADRF6620ACPZ-R7 datasheet(24/52 Pages) AD

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ADRF6620

Data Sheet

Rev. 0 | Page 24 of 52

THEORY OF OPERATION

The ADRF6620 integrates the essential elements of a multi-

channel loopback receiver that is typically used in digital

predistortion systems. The main features of the ADRF6620

include a single-pole four throw (SP4T) RF input switch with

tunable balun, variable attenuation, a wideband active mixer,

and digitally programmable variable gain amplifier (DGA).

In addition, the ADRF6620 integrates a local oscillator (LO)

generation block consisting of a synthesizer and a multicore

voltage controlled oscillator (VCO) with an octave range and

low phase noise. The synthesizer uses a fractional-N phase-locked

loop (PLL) to enable continuous LO coverage from 350 MHz to

2850 MHz.

Putting all the building blocks of the ADRF6620 together,

the signal path through the device starts at the RF input, where

one of four single-ended RF inputs is selected by the input mux

and converted to a differential signal via a tunable balun. The

differential RF signal is attenuated to an optimal input level via

the digital step attenuator with 15 dB of attenuation range in steps

of 1 dB. The RF signal is then mixed via a Gilbert cell mixer with

the LO signal down to an IF frequency. The 255 Ω terminated

differential output of the mixer is brought off chip to a pair of

inductors and passed through an IF filter. The output of the IF

filter is ac-coupled off chip and fed to an on-chip digital attenuator

and IF DGA. The output of the IF DGA is then passed to an

off-chip analog-to-digital converter (ADC).

RF INPUT SWITCHES

The ADRF6620 integrates a SP4T switch where one of four RF

inputs is selected. The desired RF input can be selected using

either pin control or register writes via the SPI. Compared to the

serial write approach, pin control allows faster control over the

switch. When the RFSW0 pin (Pin 38) and the RFSW1 pin

(Pin 39) are used, the RF switches can switch at speeds of up to

100 ns. When serial port control is used, the switch time is 100 ns,

plus the latency of the SPI programming.

The RFSW_MUX bit (Register 0x23, Bit 11) selects whether the

RF input switch is controlled via the external pins or the SPI port.

By default at power-up, the device is configured for serial control.

Writing to the RFSW_SEL bits (Register 0x23, Bits[10:9]) allows

selection of one of the four RF inputs. Alternatively, by setting

the RFSW_MUX bit high, the RFSW0 and RFSW1 pins can be

used to select the RF input. Table 10 summarizes the different

control options for the RF inputs.

To maintain good channel-to-channel isolation, ensure that unused

RF inputs are properly terminated. The RFINx ports are internally

terminated with 50 Ω resistors and have a dc bias level of 2.5 V.

To avoid disrupting the dc level, the recommended termination

is a dc blocking capacitor to GND. Figure 66 shows the recom-

mended configuration when only RFIN0 is used, and the other

RF input ports are properly terminated.

RFIN0

RFIN1

RFIN2

RFIN3

0.1µF

50Ω

Figure 66. Terminating Unused RF Input Ports

Table 10. RF Input Selection Table

RFSW_MUX (Register Address 0x23[11])

SPI Control, RFSW_SEL

(Register Address 0x23[10:9])

Pin Control

Bit 11

Bit 10

Bit 9

RFSW1, Pin 39

RFSW0, Pin 38

RF Input

RFIN0

RFIN1

RFIN2

RFIN3

RFIN0

RFIN1

RFIN2

RFIN3

X = don’t care.

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