ADRF6620ACPZ-R7 datasheet(38/52 Pages) AD

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ADRF6620

Data Sheet

Rev. 0 | Page 38 of 52

IF DGA VS. LOAD

By design, the IF DGA is optimized for performance in a matched

condition where the source and load resistances are both 150 Ω.

If the load or the source resistance is not equal to 150 Ω (see the

Digitally Programmable Variable Gain Amplifier (DGA) section),

use the following equations to determine the resulting gain and

input/output resistances:

Voltage Gain = AV = 0.044 × (1000||RL)

RIN = (1000 + RL)/(1 + 0.044 × RL)

S21 (Gain) = 2 × RIN/(RIN + RS) × AV

ROUT = (1000 + RS)/(1 + 0.044 × RS)

In a configuration where the mixer outputs of the ADRF6620

are routed to the IF DGA inputs, the matched condition is no

longer satisfied because the source impedance, as seen by the IF

DGA, is the 255 Ω output impedance of the mixer outputs. As a

result, the gain and output resistance of the amplifier vary from

the expected 15 dB (see Figure 94).

255Ω

RIN

ROUT

Figure 94. Mixer Loading of the IF DGA

The ideal load is 150 Ω for the matched condition; however, this

may not be the most readily available load impedance.

As a result, load vs. performance trade-offs must be considered.

In the matched condition, the IF DGA is optimized for linearity;

therefore, the third-order intermodulation product degrades with

load. Table 18 shows some common output loads, and Figure 95,

Figure 96, and Figure 97 show the effects of loading on gain,

IMD2, and IMD3.

As the equations in this section indicate, the manner in which

the IF DGA is loaded affects the input resistance, RIN, of the

amplifier. RIN, in turn, determines the load resistance of the

interstage filter between the mixer outputs and the IF DGA

inputs. The interstage filter has a source impedance of 255 Ω from

the mixer outputs and a load impedance of RIN for the particular

RL load (see Table 18). As a result of the impedance mismatch,

the insertion loss of the interstage filter must be included in the

level planning calculations.

100

200

300

400

500

600

700

800

900

1000

FREQUENCY (MHz)

RL = 150Ω

RL = 500Ω

RL = 73Ω

RL = 50Ω

Figure 95. IF DGA Gain vs. Frequency for Different Loads

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

120

200

280

360

440

520

600

680

FREQUENCY (MHz)

RL = 150Ω

RL = 500Ω

RL = 73Ω

RL = 50Ω

Figure 96. IF DGA IMD3 vs. Frequency for Different Loads

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

FREQUENCY (MHz)

150

Ω LOAD

500

Ω LOAD

Figure 97. IF DGA IMD2 vs. Frequency for Different Loads

Table 18. Common Output Loads

RS (Ω)

RIN (Ω)

AV (Linear)

AV (dB)

S21 (Linear)

S21 (dB)

ROUT (Ω)

RL (Ω)

255

14.7

23.3

15.5

102.7

500

255

151

5.7

15.2

4.3

12.6

102.7

150

255

9.5

102.7

255

328

2.1

6.4

2.4

7.5

102.7

ADRF6620ACPZ-R7 Datasheet(PDF) 38 Page - Analog Devices

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