ADRF6620ACPZ-R7 datasheet(26/52 Pages) AD

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ADRF6620

Data Sheet

Rev. 0 | Page 26 of 52

LO GENERATION BLOCK

The ADRF6620 offers two modes for sourcing the LO signal to

the mixer. The first mode uses the on-chip PLL and VCO. This

mode of operation provides a high quality LO that meets the

performance requirements of most applications. Using the on-

chip synthesizer and VCO removes the burden of generating

and distributing a high frequency LO signal.

The second mode bypasses the integrated LO generation block

and allows the LO to be supplied externally. This second mode

can provide a very high quality signal directly to the mixer core.

Sourcing the LO signal externally may be necessary in demanding

applications that require the lowest possible phase noise

performance.

External LO Mode

External or internal LO mode can be selected via the VCO_SEL

bits (Register 0x22, Bits[2:0]). To configure for external LO mode,

set Register 0x22, Bits[2:0] to 011 and apply the differential LO

signals to Pin 44 (LOIN−) and Pin 45 (LOIN+). The external LO

frequency range is 350 MHz to 3.2 GHz. The ADRF6620 offers the

flexibility of using a higher LO frequency signal and dividing it

down before it drives the mixer. The LO divider can be found in

the LO_DIV_A bits (Register 0x22, Bits[4:3]), where options

include ÷1, ÷2, ÷4, or ÷8.

The external LO input pins present a broadband differential 50 Ω

input impedance. The LOIN+ and LOIN− input pins must be

ac-coupled. When not in use, LOIN+ and LOIN− can be left

unconnected.

Internal LO Mode

The ADRF6620 includes an on-chip VCO and PLL for LO

synthesis. The PLL, shown in Figure 69, consists of a reference

input, phase and frequency detector (PFD), charge pump, and a

programmable integer divider with prescaler. The reference path

takes in a reference clock and divides it down by a factor of 1, 2, 4,

or 8 or multiplies it by a factor of 2 before passing it to the PFD.

The PFD compares this signal to the divided down signal from the

VCO. Depending on the PFD polarity selected, the PFD sends an

up/down signal to the charge pump if the VCO signal is slow/fast

compared to the reference frequency. The charge pump sends

a current pulse to the off-chip loop filter to increase or decrease

the tuning voltage (VTUNE).

The ADRF6620 integrates three VCO cores that cover an octave

range from 2.8 GHz to 5.7 GHz. Table 11 summarizes the fre-

quency range for each VCO. The desired VCO can be selected

by addressing the VCO_SEL bits (Register 0x22, Bits[2:0]).

Table 11. VCO Range

VCO_SEL (Register 0x22, Bits[2:0])

Frequency Range (GHz)

000

5.2 to 5.7

001

4.1 to 5.2

010

2.8 to 4.1

011

External LO

The N-divider divides down the differential VCO signal to the PFD

frequency. The N-divider can be configured for fractional mode or

integer mode by addressing the DIV_MODE bit (Register 0x02,

Bit 11). The default configuration is set for fractional mode.

PFD

CHARGE

PUMP

÷2

N = INT +

FRAC

MOD

÷1, ÷2,

÷4, ÷8

LOIN–

VTUNE

EXTERNAL

LOOP

FILTER

LPF

LOIN+

VCO_SEL

REG 0x22[2:0]

LO_DIV_A

REG 0x22[4:3]

DIV_MODE: REG 0x02[11]

INT_DIV: REG 0x02[10:0]

FRAC_DIV: REG 0x03[10:0]

MOD_DIV: REG 0x04[10:0]

CP_CTRL

REG 0x20[13:0]

×1

×2

÷8

÷4

÷2

REFIN

REFSEL

REG 0x21[2:0]

PFD_POLARITY

REG 0x21[3]

LOOUT+

TO MIXER

LOOUT–

TO MIXER

Figure 69. LO Generation Block Diagram

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