ADRF6620ACPZ-R7 datasheet(8/52 Pages) AD

No. de pieza	ADRF6620ACPZ-R7

Descripción Electrónicos	700 MHz to 2700 MHz Rx Mixer with Integrated IF DGA, Fractional-N PLL, and VCO

PDF	52 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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8 / 52 page

ADRF6620

Data Sheet

Rev. 0 | Page 8 of 52

DIGITAL LOGIC SPECIFICATIONS

Table 6.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SERIAL PORT INTERFACE TIMING

Input Voltage High

VIH

1.4

Input Voltage Low

VIL

0.70

Output Voltage High

VOH

IOH = −100 µA

2.3

Output Voltage Low

VOL

IOL = +100 µA

0.2

Serial Clock Period

tSCLK

Setup Time Between Data and Rising Edge of SCLK

tDS

Hold Time Between Data and Rising Edge of SCLK

tDH

Setup Time Between Falling Edge of CS and SCLK

Hold Time Between Rising Edge of CS and SCLK

Minimum Period SCLK Can Be in Logic High State

tHIGH

Minimum Period SCLK Can Be in Logic Low State

tLOW

Maximum Time Delay Between Falling Edge of SCLK and Output

Data Valid for a Read Operation

tACCESS

231

Maximum Time Delay Between CS Deactivation and SDIO Bus

Return to High Impedance

Timing Diagram

tDS

tDH

tHIGH

tLOW

tSCLK

DON'T CARE

D15

D14

D13

DON'T CARE

SCLK

SDIO

R/W

tACCESS

Figure 2. Serial Port Interface Timing

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