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UPD17708 Datasheet(PDF) 298 Page - NEC

No. de pieza UPD17708
Descripción Electrónicos  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD17708 Datasheet(HTML) 298 Page - NEC

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20.2.7 If two or more releasing conditions are specified at same time
If two or more halt releasing conditions are specified at same time, the halt status is released when one of the
conditions is satisfied.
The following program example shows how the releasing conditions are identified if two or more conditions are
satisfied at the same time.
Example
HLTINT
DAT
1000B
HLTBTM
DAT
0010B
HLTP0D
DAT
0001B
P0D
MEM
0.73H
START:
BR
MAIN
;*** Interrupt vector address ***
NOP
; SI01
NOP
; SI00
NOP
; TIMER3
NOP
; TIMER2
NOP
; TIMER1
NOP
; TIMER0
NOP
; INT4
NOP
; INT3
NOP
; INT2
NOP
; INT1
BR
INT0
; Branches to INT0 interrupt processing
NOP
; CE DOWN EDGE
INT0:
; INT0 pin interrupt vector address (000BH)
Processing A
; INT0 pin interrupt processing
EI
RETI
BTMOUP:
; Timer carry FF processing
Processing B
RET
P0DP:
; P0D input processing
Processing C
RET
MAIN:
INITFLG NOT BTM0CK1, NOT BTM0CK0
; Selects 100 ms as clock of basic timer 0
SET1
IP0
; Enables INT0 pin interrupt
EI
LOOP:
HALT HLTINT OR HLTBTM OR HLTP0C
; Selects interrupt, timer carry FF, and P0D input as halt releasing conditions
SKF1
BTM0CY
; Detects BTM0CY flag
CALL
BTM0UP
; Timer carry FF processing if flag is set to 1
SKF
P0D, 1111B
; Detects P0D input
CALL
P0DP
; Port input processing if P0D is high
BR
LOOP



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