UPD17708 datasheet(303/356 Pages) NEC

303 / 356 page

303

µPD17704, 17705, 17707, 17708, 17709

Table 20-2. Status of Each Pin in Halt and Clock Stop Status and Cautions (2/2)

Pin Function

Pin Symbol

Status of Each Pin and Cautions on Processing

Halt status

Clock stop status

External interrupt

INT4-INT0

Current consumption increases due to noise if pin is floated

PLL frequency

VCOL

synthesizer

VCOH

EO0

EO1

Crystal oscillation

XIN

circuit

XOUT

20.6 Device Operation Control Function of CE Pin

The CE pin controls the following functions by the input level and rising edge of the signal input from an external

source.

•

PLL frequency synthesizer

•

Interrupt by falling edge of CE pin

•

Resetting of device

20.6.1 Controlling operation of PLL frequency synthesizer

The PLL frequency synthesizer can operate only when the CE pin is high.

It is automatically disabled when the CE pin is low.

When the synthesizer is disabled, the VCOH and VCOL pins are internally pulled down, and the EO0 and EO1

pins are floated. For details, refer to 17.5 PLL Disabled Status.

The PLL frequency synthesizer can be disabled in software even when the CE pin is high.

20.6.2 Controlling interrupt by falling edge input of CE pin

An interrupt can be generated by the falling edge of the CE pin. For details, refer to 12. INTERRUPTS.

Current consumption increases during PLL

operation.

When PLL is disabled, pin is in following

status:

VCOH, VCOL : internally pulled down

EO1, EO0

: floated

PLL is automatically disabled if CE pin

goes low

PLL is disabled

VCOH, VCOL : internally pulled down

EO1, EO0

: floated

Current consumption changes due to

oscillation waveform of crystal oscillation

circuit.

The higher oscillation amplitude, the lower

current consumption.

Oscillation amplitude must be evaluated

because it is influenced by crystal resonator

or load capacitor used

XIN pin is internally pulled down, and XOUT

pin outputs high level

UPD17708 Datasheet(PDF) 303 Page - NEC

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