UPD17708 datasheet(299/356 Pages) NEC

299 / 356 page

299

µPD17704, 17705, 17707, 17708, 17709

In the above example, three halt status releasing conditions, INT0 pin interrupt, 100-ms basic timer 0 carry FF, and

port 0D input, are specified.

To identify which condition has released the halt status, a vector address (interrupt), BTM0CY flag (timer carry FF),

and port register (port input) are detected.

To use two or more releasing conditions, the following two points must be noted.

•

When the halt status is released, all the specified releasing conditions must be detected.

•

The releasing condition with the higher priority must be detected first.

20.3 Clock Stop Function

20.3.1 Outline of clock stop function

The clock stop function stops the oscillation circuit of a 4.5-MHz crystal resonator by executing the “STOP s”

instruction (clock stop status).

Therefore, the current consumption of the device is reduced to 30

µA MAX.

20.3.2 Clock stop status

In the clock stop status, all the device operations of the CPU and peripheral hardware units are stopped because

the generation circuit of the crystal resonator is stopped.

For the operations of the CPU and peripheral hardware units, refer to 20.4 Device Operation in Halt and Clock

Stop Status.

In the clock stop status, the power failure detection circuit does not operate even if the supply voltage VDD of the

device is raised to 2.2 V. Therefore, the data memory can be backed up at a low voltage. For the power failure detection

circuit, refer to 21. RESET.

20.3.3 Releasing clock stop status

Figure 20-3 shows the stop status releasing conditions.

The stop status releasing condition is specified by 4-bit data specified by operand “s” of the “STOP s” instruction.

The stop status is released when the condition specified by “1” in operand “s” is satisfied.

When the stop status has been released, a halt period which is half the time (tSET/2) specified by the basic timer

0 clock selection register as oscillation circuit stabilization wait time has elapsed, and the program execution is started

from the instruction next to the “STOP s” instruction. If releasing the stop status by an interrupt is specified, however,

the program operation after the stop status has been released differs depending on whether the interrupt is enabled

(EI status) or disabled (DI status) when an interrupt source is issued (IRQxxx = 1) with the interrupt enabled (IPxxx

= 1).

If all the interrupts are enabled (EI status), the stop status is released when the interrupt is enabled (IPxxx = 1)

and the interrupt source is issued (IRQxxx = 1), and the program flow returns to the instruction next to the STOP

instruction.

If all the interrupts are disabled (DI status), the stop status is released when the interrupt is enabled (IPxxx = 1)

and the interrupt resource is issued (IRQxxx = 1), and the program flow returns to the instruction next to the STOP

instruction.

If two or more releasing conditions are specified at one time, and if one of the conditions is satisfied, the stop status

is released.

If 0000B is specified as stop releasing condition “s”, no releasing condition is satisfied. If the device is reset at

this time (by means of power-ON reset, or CE reset), the stop status is released.

UPD17708 Datasheet(PDF) 299 Page - NEC

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