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UPD17708 Datasheet(PDF) 300 Page - NEC |
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UPD17708 Datasheet(HTML) 300 Page - NEC |
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300 / 356 page  300 µPD17704, 17705, 17707, 17708, 17709 Figure 20-3. Stop Releasing Conditions Operand STOP s (4 bits) b3 b2 b1 b0 0 1 Releases when high level is input to port 0D Undefined (Fix this bit to “0”.) Undefined (Fix this bit to “0”.) Released by interrupt of falling edge of INT0 through INT4 pins and CE pin Not released even if condition is statisfied Released if condition is satisfied Specifies stop status releasing condition The “STOP s” instruction is executed as a “NOP” instruction when the CE pin rises and when the CE reset counter operates. The operating status of the CE reset counter can be detected by the CECNTSTT flag (for the CE reset counter, refer to 21. RESET). 20.3.4 Releasing clock stop status by high level input of port 0D Figure 20-4 illustrates how the clock stop status is released by the high level input to port 0D. Figure 20-4. Releasing Clock Stop Status By High Level Input of Port 0D VDD P0D XOUT 5 V 0 V H L 2.2 V STOP s instruction Starts from instruction next to STOP s Oscillation stops tSET/2 HALT period tSET: basic timer 0 setting time 20.3.5 Cautions on releasing clock stop status For the cautions on releasing the clock stop status, refer to (2) Releasing from clock stop status in 21.4.4 Cautions on raising supply voltage VDD. |
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