UPD17708 datasheet(301/356 Pages) NEC

301 / 356 page

301

µPD17704, 17705, 17707, 17708, 17709

20.4 Device Operation in Halt and Clock Stop Status

Table 20-1 shows the operations of the CPU and peripheral hardware units in the halt and clock stop status.

In the halt status, all the peripheral hardware units continue the normal operation until instruction execution is

stopped.

In the clock stop status, all the peripheral hardware units stop operation.

The control registers that control the operations of the peripheral hardware units operate normally (not initialized)

in the halt status, but are initialized to specified values when the clock stop instruction is executed.

In other words, all peripheral hardware continues the operation specified by the control register in the halt status,

and the operation is determined by the initialized value of the control register in the clock stop status.

For the values of the control registers in the clock stop status, refer to 8. REGISTER FILE (RF).

Table 20-1. Device Operation in Halt and Clock Stop Status

Peripheral Hardware

Status

Halt

Clock stop

Program counter

Stops at address of HALT instruction

Stops at address of STOP instruction

System register

Retained

Peripheral register

Retained

Partly initializedNote 1

Control register

Retained

Partly initializedNote 1

Timer

Normal operation

Operation stops

PLL frequency synthesizer

Normal operationNote 2

Operation stops

A/D converter

Normal operation

Operation stops

D/A converter

Normal operation

Stops operation and used as general-

purpose output port

Serial interface

Stops operation when internal clock (master)

Stops operation and used as general-

is selected and continues operation when

purpose I/O port

external clock (slave) is selected

Frequency counter

Normal operation

Stops operation and used as general-

purpose input port

BEEP output

Normal operation

Stops operation and used as general-

purpose I/O port

General-purpose I/O port

Normal operation

Retained

General-purpose input port

Normal operation

Input port

General-purpose output port

Normal operation

Retains output latch

Notes 1. For the value to which these registers are initialized, refer to 5. SYSTEM REGISTER (SYSREG) and

8. REGISTER FILE (RF).

2. The PLL frequency synthesizer is automatically disabled by the low level input to the CE pin.

20.5 Cautions on Processing of Each Pin in Halt and Clock Stop Status

The halt status is used to reduce the current consumption when, say, only the watch is used.

The clock stop function is used to reduce the current consumption of the device to only use the data memory.

Therefore, the current consumption must be reduced as much as possible in the halt status or clock stop status.

At this time, the current consumption significantly varies depending on the status of each pin, and the points shown

in Table 20-2 must be noted.

UPD17708 Datasheet(PDF) 301 Page - NEC

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