ADE7758_15 datasheet(40/72 Pages) AD

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ADE7758

Data Sheet

Rev. E | Page 40 of 72

Apparent Energy Calculation

Apparent energy is defined as the integral of apparent power.

Apparent Energy = ∫ S(t)dt

(41)

Similar to active or reactive power accumulation, the fastest

integration time occurs when the VAGAIN registers are set to

maximum full scale, that is, 0x7FF. When overflow occurs, the

content of the VA-hr accumulation registers can roll over to 0

and continue increasing in value.

Similar to active and reactive energy, the ADE7758 achieves the

integration of the apparent power signal by continuously

accumulating the apparent power signal in the internal 41-bit,

unsigned accumulation registers. The VA-hr registers (AVAHR,

BVAHR, and CVAHR) represent the upper 16 bits of these

internal registers. This discrete time accumulation or

summation is equivalent to integration in continuous time.

Equation 42 expresses the relationship

By setting the VAEHF bit (Bit 2) of the mask register, the ADE7758

can be configured to issue an interrupt (IRQ) when the MSB of

any one of the three VA-hr accumulation registers has changed,

indicating that the accumulation register is half full.

Setting the RSTREAD bit (Bit 6) of the LCYMODE register

enables a read-with-reset for the VA-hr accumulation registers;

that is, the registers are reset to 0 after a read operation.

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

Energy

Apparent

(42)

Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation register

is 0.4 μs (4/CLKIN). With full-scale, 60 Hz sinusoidal signals on

the analog inputs and the VAGAIN registers set to 0x000, the

average word value from each LPF2 is 0xB9954. The maximum

value that can be stored in the apparent energy register before it

overflows is 216 − 1 or 0xFFFF. As the average word value is first

added to the internal register, which can store 241 − 1 or 0x1FF,

FFFF, FFFF before it overflows, the integration time under these

conditions with VADIV = 0 is calculated as

where:

n is the discrete time sample number.

T is the sample period.

Figure 76 shows the signal path of the apparent energy accumu-

lation. The apparent power signal is continuously added to the

internal apparent energy register. The average apparent power is

divided by the content of the VA divider register before it is

added to the corresponding VA-hr accumulation register. When

the value in the VADIV[7:0] register is 0 or 1, apparent power is

accumulated without any division. VADIV is an 8-bit unsigned

VA-hr accumulation registers overflow.

sec

1.157

μs

0.4

0xB9954

FFFF

FFFF,

0x1FF,

Time

(43)

When VADIV is set to a value different from 0, the time before

overflow is scaled accordingly, as shown in Equation 44.

Time = Time(VADIV = 0) × VADIV

(44)

VOLTAGE RMS SIGNAL

0x174BAC

60Hz

0x0

0x17F263

50Hz

0x0

CURRENT RMS SIGNAL

0x1C82B

0x00

MULTIPLIER

IRMS

VRMS

VAG[11:0]

VADIV[7:0]

LPF2

VARHR[15:0]

APPARENT POWER IS

ACCUMULATED (INTEGRATED) IN

THE VA-HR ACCUMULATION REGISTERS

Figure 76. ADE7758 Apparent Energy Accumulation

ADE7758 Datasheet(PDF) 40 Page - Analog Devices

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