ADE7758_15 datasheet(6/72 Pages) AD

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ADE7758

Data Sheet

Rev. E | Page 6 of 72

Parameter1, 2

Specification

Unit

Test Conditions/Comments

LOGIC OUTPUTS

DVDD = 5 V ± 5%

IRQ, DOUT, and CLKOUT

IRQ is open-drain, 10 kΩ pull-up resistor

Output High Voltage, VOH

V min

ISOURCE = 5 mA

Output Low Voltage, VOL

0.4

V max

ISINK = 1 mA

APCF and VARCF

Output High Voltage, VOH

V min

ISOURCE = 8 mA

Output Low Voltage, VOL

V max

ISINK = 5 mA

POWER SUPPLY

For specified performance

AVDD

4.75

V min

5 V − 5%

5.25

V max

5 V + 5%

DVDD

4.75

V min

5 V − 5%

5.25

V max

5 V + 5%

AIDD

mA max

Typically 5 mA

DIDD

mA max

Typically 9 mA

1 See the Typical Performance Characteristics.

2 See the Terminology section for a definition of the parameters.

3 See the Analog Inputs section.

TIMING CHARACTERISTICS

AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C.

Table 2.

Parameter1, 2

Specification

Unit

Test Conditions/Comments

WRITE TIMING

ns (min)

CS falling edge to first SCLK falling edge

ns (min)

SCLK logic high pulse width

ns (min)

SCLK logic low pulse width

ns (min)

Valid data setup time before falling edge of SCLK

ns (min)

Data hold time after SCLK falling edge

1200

ns (min)

Minimum time between the end of data byte transfers

400

ns (min)

Minimum time between byte transfers during a serial write

100

ns (min)

CS hold time after SCLK falling edge

READ TIMING

t93

μs (min)

Minimum time between read command (that is, a write to communication register) and

data read

t10

ns (min)

Minimum time between data byte transfers during a multibyte read

t114

ns (min)

Data access time after SCLK rising edge following a write to the communications register

t125

100

ns (max)

Bus relinquish time after falling edge of SCLK

ns (min)

t135

100

ns (max)

Bus relinquish time after rising edge of CS

ns (min)

1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to

90%) and timed from a voltage level of 1.6 V.

2 See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section.

3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.

4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted here is the true bus relinquish time of the part and is

independent of the bus loading.

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