ADE7758_15 datasheet(41/72 Pages) AD

41 / 72 page

Data Sheet

ADE7758

Rev. E | Page 41 of 72

Table 14. Inputs to VA-Hr Accumulation Registers

CONSEL[1, 0]

AVAHR1

BVAHR

CVAHR

AVRMS × AIRMS

BVRMS × BIRMS

CVRMS × CIRMS

AVRMS × AIRMS

AVRMS + CVRMS/2 × BIRMS

CVRMS × CIRMS

AVRMS × AIRMS

BVRMS × BIRMS

CVRMS × CIRMS

Reserved

1 AVRMS/BVRMS/CVRMS are the rms voltage waveform, and AIRMS/BIRMS/CIRMS are the rms values of the current waveform.

Energy Accumulation Mode

The apparent power accumulated in each VA-hr accumulation

figuration of the CONSEL bits in the COMPMODE register

(Bit 0 and Bit 1). The different configurations are described in

Table 14.

The contents of the VA-hr accumulation registers are affected

by both the registers for rms voltage gain (VRMSGAIN), as well

as the VAGAIN register of the corresponding phase.

Apparent Power Frequency Output

Pin 17 (VARCF) of the ADE7758 provides frequency output for

the total apparent power. By setting the VACF bit (Bit 7) of the

WAVMODE register, this pin provides an output frequency that

is directly proportional to the total apparent power.

A digital-to-frequency converter (DFC) is used to generate the

pulse output from the total apparent power. The TERMSEL bits

(Bit 2 to Bit 4) of the COMPMODE register can be used to

select which phases to include in the total power calculation.

Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVAHR,

BVAHR, and CVAHR registers in the total apparent power

calculation. A pair of frequency divider registers, namely

VARCFDEN and VARCFNUM, can be used to scale the output

frequency of this pin. Note that either VAR or apparent power

can be selected at one time for this frequency output (see the

Reactive Power Frequency Output section).

Line Cycle Apparent Energy Accumulation Mode

The line cycle apparent energy accumulation mode is activated

by setting the LVA bit (Bit 2) in the LCYCMODE register. The

total apparent energy accumulated over an integer number of

zero crossings is written to the VA-hr accumulation registers

after the LINECYC number of zero crossings is detected. The

operation of this mode is similar to watt-hr accumulation (see

the Line Cycle Active Energy Accumulation Mode section).

When using the line cycle accumulation mode, the RSTREAD

bit (Bit 6) of the LCYCMODE register should be set to Logic 0.

Note that this mode is especially useful when the user chooses

to perform the apparent energy calculation using the vectorial

method.

By setting LWATT and LVAR bits (Bit 0 and Bit 1) of the

LCYCMODE register, the active and reactive energies are

accumulated over the same period. Therefore, the MCU can

perform the squaring of the two terms and then take the square

root of their sum to determine the apparent energy over the

same period.

ENERGY REGISTERS SCALING

The ADE7758 provides measurements of active, reactive, and

apparent energies that use separate signal paths and filtering for

calculation. The differences in the datapaths can result in small

differences in LSB weight between the active, reactive, and

apparent energy registers. These measurements are internally

compensated so that the scaling is nearly one to one. The

relationship between the registers is shown in Table 15.

Table 15. Energy Registers Scaling

Frequency

60 Hz

50 Hz

Integrator Off

VAR

1.004 × WATT

1.0054 × WATT

1.00058 × WATT

1.0085 × WATT

Integrator On

VAR

1.0059 × WATT

1.0064 × WATT

1.00058 × WATT

1.00845 × WATT

WAVEFORM SAMPLING MODE

The waveform samples of the current and voltage waveform, as

well as the active, reactive, and apparent power multiplier out-

puts, can all be routed to the WAVEFORM register by setting

the WAVSEL[2:0] bits (Bit 2 to Bit 4) in the WAVMODE

setting the PHSEL[1:0] bits (Bit 0 and Bit 1) in the WAVMODE

waveform sampling. Four output sample rates can be chosen by

using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]).

The output sample rate can be 26.04 kSPS, 13.02 kSPS,

6.51 kSPS, or 3.25 kSPS (see Table 20).

By setting the WFSM bit in the interrupt mask register to

Logic 1, the interrupt request output IRQ goes active low when

a sample is available. The 24-bit waveform samples are

transferred from the ADE7758 one byte (8 bits) at a time, with

the most significant byte shifted out first.

The interrupt request output IRQ stays low until the interrupt

routine reads the reset status register (see the Interrupts section).

ADE7758 Datasheet(PDF) 41 Page - Analog Devices

ADE7758 Datasheet(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Descarga

Enlace URL