ADE7758_15 datasheet(25/72 Pages) AD

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Data Sheet

ADE7758

Rev. E | Page 25 of 72

PGA1

IAP

IAN

ADC

HPF

PGA2

VAP

ADC

60Hz

0.1°

RANGE OF PHASE

CALIBRATION

111 110 0

APHCAL[6:0]

–153.6µs TO +75.6µs

VA ADVANCED BY 4.8µs

(+0.104

° @ 60Hz)

0x7E

60Hz

DIGITAL

INTEGRATOR

ACTIVE AND

REACTIVE

ENERGY

CALCULATION

+1.36°, –2.76° @ 50Hz; 0.022°, 0.043°

+1.63°, –3.31° @ 60Hz; 0.026°, 0.052°

Figure 56. Phase Calibration on Voltage Channels

PERIOD MEASUREMENT

The ADE7758 provides the period or frequency measurement

of the line voltage. The period is measured on the phase

specified by Bit 0 to Bit 1 of the MMODE register. The period

every four periods of the selected phase.

Bit 7 of the LCYCMODE selects whether the period register

displays the frequency or the period. Setting this bit causes the

which causes the register to display the frequency.

When set to measure the period, the resolution of this register is

96/CLKIN per LSB (9.6 μs/LSB when CLKIN is 10 MHz),

which represents 0.06% when the line frequency is 60 Hz. At

60 Hz, the value of the period register is 1737d. At 50 Hz, the

value of the period register is 2084d. When set to measure

frequency, the value of the period register is approximately 960d at

60 Hz and 800d at 50 Hz. This is equivalent to 0.0625 Hz/LSB.

LINE VOLTAGE SAG DETECTION

The ADE7758 can be programmed to detect when the absolute

value of the line voltage of any phase drops below a certain peak

value for a number of half cycles. Each phase of the voltage

channel is controlled simultaneously. This condition is

illustrated in Figure 57.

Figure 57 shows a line voltage fall below a threshold, which is

set in the SAG level register (SAGLVL[7:0]), for nine half cycles.

Because the SAG cycle register indicates a six half-cycle threshold

(SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of

the sixth half cycle by setting the SAG flag of the corresponding

phase in the interrupt status register (Bit 1 to Bit 3 in the

interrupt status register).

If the SAG enable bit is set to Logic 1 for this phase (Bit 1 to

Bit 3 in the interrupt mask register), the IRQ logic output goes

active low (see the

section). The phases are compared

to the same parameters defined in the SAGLVL and SAGCYC

registers.

Interrupts

SAGLVL[7:0]

FULL-SCALE

READ RSTATUS

SAGCYC[7:0] = 0x06

6HALF CYCLES

SAG INTERRUPT FLAG

(BIT 3 TO BIT 5 OF

STATUS REGISTER)

VAP, VBP, OR VCP

SAG EVENT RESET LOW

WHEN VOLTAGE CHANNEL

EXCEEDS SAGLVL[7:0]

Figure 57. ADE7758 SAG Detection

Figure 57 shows a line voltage fall below a threshold, which is

set in the SAG level register (SAGLVL[7:0]), for nine half cycles.

Because the SAG cycle register indicates a six half-cycle threshold

(SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of

the sixth half cycle by setting the SAG flag of the corresponding

phase in the interrupt status register (Bit 1 to Bit 3 in the

interrupt status register). If the SAG enable bit is set to Logic 1

for this phase (Bit 1 to Bit 3 in the interrupt mask register), the

IRQ logic output goes active low (see the

section).

The phases are compared to the same parameters defined in the

SAGLVL and SAGCYC registers.

Interrupts

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