ADE7758_15 datasheet(69/72 Pages) AD

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Data Sheet

ADE7758

Rev. E | Page 69 of 72

INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A)

The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the

corresponding flag in the interrupt status register is set. The IRQ pin goes active low if the corresponding bit in the interrupt mask

register is set. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the

source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after an event occurs. The state of the

interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read.

Table 24. Interrupt Status Register

Bit

Location

Interrupt

Flag

Default

Value

Event Description

AEHF

Indicates that an interrupt was caused by a change in Bit 14 among any one of the three WATTHR

registers, that is, the WATTHR register is half full.

REHF

Indicates that an interrupt was caused by a change in Bit 14 among any one of the three VARHR

registers, that is, the VARHR register is half full.

VAEHF

Indicates that an interrupt was caused by a 0 to 1 transition in Bit 15 among any one of the three VAHR

registers, that is, the VAHR register is half full.

SAGA

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A.

SAGB

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B.

SAGC

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C.

ZXTOA

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A.

ZXTOB

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B.

ZXTOC

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C.

ZXA

Indicates a detection of a rising edge zero crossing in the voltage channel of Phase A.

ZXB

Indicates a detection of a rising edge zero crossing in the voltage channel of Phase B.

ZXC

Indicates a detection of a rising edge zero crossing in the voltage channel of Phase C.

LENERGY

In line energy accumulation, indicates the end of an integration over an integer number of half-line

cycles (LINECYC). See the Calibration section.

Reset

After Bit 6 (SWRST) in OPMODE register is set to 1, the ADE7758 enters software reset. This bit

becomes 1 after 166 μsec, indicating the reset process has ended and the registers are set to their

default values. It stays 1 until the reset interrupt status register is read and then becomes 0.

PKV

Indicates that an interrupt was caused when the selected voltage input is above the value in the

VPINTLVL register.

PKI

Indicates that an interrupt was caused when the selected current input is above the value in the

IPINTLVL register.

WFSM

Indicates that new data is present in the waveform register.

REVPAP

Indicates that an interrupt was caused by a sign change in the watt calculation among any one of the

phases specified by the TERMSEL bits in the COMPMODE register.

REVPRP

Indicates that an interrupt was caused by a sign change in the VAR calculation among any one of the

phases specified by the TERMSEL bits in the COMPMODE register.

SEQERR

Indicates that an interrupt was caused by a zero crossing from Phase A followed not by the zero

crossing of Phase C but by that of Phase B.

ADE7758 Datasheet(PDF) 69 Page - Analog Devices

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