CC1021-RTR1 datasheet(16/91 Pages) TI1

16 / 91 page

DIO

LOCK

DCLK

RF_IN

LNA

FREQ

SYNTH

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

MODULATOR

- Modulation

- Data shaping

- Power Control

BIAS

Power

Control

DIGITAL

INTERFACE

TO mC

ADC

RF_OUT

R_BIAS

XOSC_Q1 XOSC_Q2

PDO

XOSC

CHP_OUT

LNA 2

Multiplexer

PA_EN

LNA_EN

PCLK

PDI

PSEL

Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

www.ti.com

Detailed Description

5.1

Overview

A simplified block diagram of CC1021 is shown in Figure 5-1. Only signal pins are shown.

CC1021 features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA

and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q

signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain control, fine

channel filtering, demodulation and bit synchronization is performed digitally. CC1021 outputs the digital

demodulated data on the DIO pin. A synchronized data clock is available at the DCLK pin. RSSI is

available in digital format and can be read via the serial interface. The RSSI also features a programmable

carrier sense indicator.

In transmit mode, the synthesized RF frequency is fed directly to the power amplifier (PA). The RF output

is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian

filter can be used to obtain Gaussian FSK (GFSK).

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for

generating the LO_I and LO_Q signals to the down-conversion mixers in receive mode. The VCO

operates in the frequency range 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and

VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal

is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.

The 4-wire SPI serial interface is used for configuration.

5.2

Functional Block Diagram

Figure 5-1. CC1021 Simplified Block Diagram

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC1021

CC1021-RTR1 Datasheet(PDF) 16 Page - Texas Instruments

CC1021-RTR1 Datasheet(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Descarga

Enlace URL