CC1021-RTR1 datasheet(21/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

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SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

5.6.1

Synchronous NRZ Mode

In transmit mode CC1021 provides the data clock at DCLK and DIO is used as data input. Data is clocked

into CC1021 at the rising edge of DCLK. The data is modulated at RF without encoding.

In receive mode CC1021 performs the synchronization and provides received data clock at DCLK and

data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See

Figure 5-6.

5.6.2

Transparent Asynchronous UART Mode

In transmit mode, DIO is used as data input. The data is modulated at RF without synchronization or

encoding.

In receive mode, the raw data signal from the demodulator is sent to the output (DIO). No synchronization

or decoding of the signal is done in CC1021 and should be done by the interfacing circuit.

If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data

input in transmit mode. The DCLK pin is not active and can be set to a high or low level by

DATA_FORMAT[0].

If SEP_DI_DO = 1 in the INTERFACE register, the DCLK pin is the data output in receive mode and the

DIO pin is the data input in transmit mode. In TX mode the DCLK pin is not active and can be set to a high

or low level by DATA_FORMAT[0]. See Figure 5-8.

5.6.3

Synchronous Manchester Encoded Mode

In transmit mode CC1021 provides the data clock at DCLK and DIO is used as data input. Data is clocked

into CC1021 at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with

Manchester code. The encoding is done by CC1021. In this mode the effective bit rate is half the baud

rate due to the coding. As an example, 19.2 kBaud Manchester encoded data corresponds to 9.6 kbps.

In receive mode CC102 performs the synchronization and provides received data clock at DCLK and data

at DIO. CC1021 performs the decoding and NRZ data is presented at DIO. The data should be clocked

into the interfacing circuit at the rising edge of DCLK. See Figure 5-7.

In synchronous NRZ or Manchester mode the DCLK signal runs continuously both in RX and TX unless

the DCLK signal is gated with the carrier sense signal or the PLL lock signal. Refer to Section 5.18 for

more details.

If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data

input in transmit mode.

As an option, the data output can be made available at a separate pin. This is done by setting

SEP_DI_DO = 1 in the INTERFACE register. Then, the LOCK pin will be used as data output in

synchronous mode, overriding other use of the LOCK pin.

5.6.3.1

Manchester Encoding and Decoding

In the Synchronous Manchester encoded mode CC1021 uses Manchester coding when modulating the

data. The CC1021 also performs the data decoding and synchronization. The Manchester code is based

on transitions; a “0” is encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition.

See Figure 5-7.

The Manchester code ensures that the signal has a constant DC component, which is necessary in some

FSK demodulators. Using this mode also ensures compatibility with CC400 and CC900 designs.

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