CC1021-RTR1 datasheet(48/91 Pages) TI1

48 / 91 page

Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

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Table 5-12. Typical PLL Turn-On Time to Within Specified Accuracy for Different Loop Filter Bandwidths

LOOP

PLL TURN-ON TIME

FILTER

COMMENT

[nF]

[pF]

Ω]

[µs]

NO.

Up to 9.6 kBaud data

rate

2200

560

3.3

1400

±5 kHz settling

accuracy

Up to 19.2 kBaud data

rate

560

150

5.6

1300

±10 kHz settling

accuracy

Up to 38.4 kBaud data

rate

3.9

120

1080

±15 kHz settling

accuracy

Up to 76.8 kBaud data

rate

1.0

3.3

950

±20 kHz settling

accuracy

Up to 153.6 kBaud data

rate

0.2

1.5

—

150

700

±50 kHz settling

accuracy

5.12.4 PLL Lock Time versus Loop Filter Bandwidth

If calibration has been performed the PLL lock time is the time needed for the PLL to lock to the desired

frequency when going from RX to TX mode or vice versa. The PLL lock time depends on the PLL loop

filter bandwidth. Table 5-13 gives the PLL lock time for different PLL loop filter bandwidths.

Table 5-13. Typical PLL Lock Time to Within Specified Accuracy for Different Loop Filter Bandwidths(1)

LOOP

PLL LOCK TIME [µs]

FILTER

COMMENT

[nF]

[pF]

Ω]

NO.

140

Up to 9.6 kBaud data rate

2200

560

3.3

400

490

(50 kHz)

±5 kHz settling accuracy

Up to 19.2 kBaud data rate

560

150

5.6

140

230

(100 kHz)

±10 kHz settling accuracy

Up to 38.4 kBaud data rate

3.9

120

180

(150 kHz)

±15 kHz settling accuracy

Up to 76.8 kBaud data rate

1.0

3.3

(200 kHz)

±20 kHz settling accuracy

Up to 153.6 kBaud data rate

0.2

1.5

—

150

(500 kHz)

±50 kHz settling accuracy

(1)

1) 307.2 kHz step,

2) step as given in brackets,

3) 1 MHz step

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