CC1021-RTR1 datasheet(12/91 Pages) TI1

12 / 91 page

Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

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4.7

Intermediate Frequency (IF)

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical

specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V, fC = 14.7456

MHz if nothing else stated.

PARAMETER

TYP

UNIT

CONDITION

Intermediate frequency (IF)

307.2

kHz

See Section 5.9.1 for details.

The channel filter 6 dB bandwidth is programmable

Digital channel filter bandwidth

38.4 to 307.2

kHz

from 9.6 kHz to 307.2 kHz. See Section 5.9.2 for

details.

At 19.2 kBaud

AFC resolution

1200

Given as Baud rate / 16. See Section 5.9.13 for

details.

4.8

Crystal Oscillator

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical

specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V, fC = 14.7456

MHz if nothing else stated.

PARAMETER

MIN

TYP

MAX

UNIT

CONDITION

Recommended frequency is

Crystal Oscillator Frequency

4.9152

14.7456

19.6608

MHz

14.7456 MHz. See

Section 5.16 for details.

C4 and C5 are loading

Crystal operation

Parallel

capacitors. See Section 5.16

for details.

4.9 to 6 MHz,

22 pF recommended

6 to 8 MHz,

Crystal load capacitance

16 pF recommended

8 to 19.6 MHz,

16 pF recommended

4.9152 MHz, 12 pF load

1.55

7.3728 MHz, 12 pF load

9.8304 MHz, 12 pF load

0.9

Crystal oscillator

start-up time

14.7456 MHz, 16 pF load

0.95

17.2032 MHz, 12 pF load

0.6

19.6608 MHz, 12 pF load

0.63

The external clock signal must

be connected to XOSC_Q1

using a DC block (10 nF). Set

XOSC_BYPASS = 0 in the

External clock signal drive, sine wave

300

mVpp

INTERFACE register when

using an external clock signal

with low amplitude or a

crystal.

The external clock signal must

be connected to XOSC_Q1.

No DC block shall be used.

External clock signal drive, full-swing digital external clock

0 – VDD

Set XOSC_BYPASS = 1 in

the INTERFACE register

when using a full-swing digital

external clock.

Specifications

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