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CC1021-RTR1 Datasheet(PDF) 73 Page - Texas Instruments |
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CC1021-RTR1 Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 91 page ![]() Not Recommended for New Designs NRND CC1021 www.ti.com SWRS045D – JANUARY 2006 – REVISED JANUARY 2015 Table 5-44. PLL_BW Register (1Ah) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE PLL_BW[7:0] PLL_BW[7:0] 134 — Charge pump current scaling/rounding factor. Used to calibrate charge pump current for the desired PLL loop bandwidth. The value is given by: PLL_BW = 174 + 16 log2(fref / 7.126) where fref is the reference frequency in MHz. Table 5-45. CALIBRATE Register (1Bh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE CALIBRATE[7] CAL_START 0 ↑ ↑ 1: Calibration started 0: Calibration inactive CALIBRATE[6] CAL_DUAL 0 H Use calibration results for both frequency A and B 0: Store results in A or B defined by F_REG (MAIN[6]) 1: Store calibration results in both A and B CALIBRATE[5:4] CAL_WAIT[1:0] 0 — Selects calibration wait time (affects accuracy) 0 (00): Calibration time is approx. 90000 F_REF periods 1 (01): Calibration time is approx. 110000 F_REF periods 2 (10): Calibration time is approx. 130000 F_REF periods 3 (11): Calibration time is approx. 200000 F_REF periods Recommended setting: CAL_WAIT=3 for best accuracy in calibrated PLL loop filter bandwidth. CALIBRATE[3] — 0 — Reserved, write 0 CALIBRATE[2:0] CAL_ITERATE[2:0] 5 — Iteration start value for calibration DAC 0 (000): DAC start value 1, VC < 0.49 V after calibration 1 (001): DAC start value 2, VC < 0.66 V after calibration 2 (010): DAC start value 3, VC < 0.82 V after calibration 3 (011): DAC start value 4, VC < 0.99 V after calibration 4 (100): DAC start value 5, VC < 1.15 V after calibration 5 (101): DAC start value 6, VC < 1.32 V after calibration 6 (110): DAC start value 7, VC < 1.48 V after calibration 7 (111): DAC start value 8, VC < 1.65 V after calibration Recommended setting: CAL_ITERATE=4. Table 5-46. PA_POWER Register (1Ch) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE PA_POWER[7:4] PA_HIGH [3:0] 0 — Controls output power in high-power array 0: High-power array is off 1: Minimum high-power array output power … 15: Maximum high-power array output power PA_POWER[3:0] PA_LOW[3:0] 15 — Controls output power in low-power array 0: Low-power array is off 1: Minimum low-power array output power … 15: Maximum low-power array output power It is more efficient in terms of current consumption to use either the lower or upper 4-bits in the PA_POWER register to control the power. Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 73 Submit Documentation Feedback Product Folder Links: CC1021 |
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