CC1021-RTR1 datasheet(34/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

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To avoid unnecessary tripping of the VGA, an extra hysteresis and filtering of the RSSI samples can be

added. The AGC_HYSTERESIS bit in the VGA2 register enables this.

The time dynamics of the loop can be altered by the VGA_BLANKING bit in the ANALOG register, and

VGA_FREEZE[1:0] and VGA_WAIT[2:0] bits in the VGA1 register.

When VGA_BLANKING is activated, the VGA recovery time from DC offset spikes after a gain step is

reduced.

VGA_FREEZE determines the time to hold bit synchronization, VGA and RSSI levels after one of these

events occur:

•

RX power-up

•

The PLL has been out of lock

•

Frequency register setting is switched between A and B

This feature is useful to avoid AGC operation during start-up transients and to ensure minimum dwell time

using frequency hopping. This means that bit synchronization can be maintained from hop to hop.

VGA_WAIT determines the time to hold the present bit synchronization and RSSI levels after changing

VGA gain. This feature is useful to avoid AGC operation during the settling of transients after a VGA gain

change. Some transients are expected due to DC offsets in the VGA.

At the sensitivity limit, the VGA gain is set by VGA_SETTING. In order to optimize selectivity, this gain

should not be set higher than necessary. The SmartRF Studio software gives the settings for VGA1

through VGA4 registers. For reference, the following method can be used to find the AGC settings:

1. Disable AGC and use maximum LNA2 gain by writing BFh to the VGA2 register. Set minimum VGA

gain by writing to the VGA3 register with VGA_SETTING = 0.

2. Apply no RF input signal, and measure ADC noise floor by reading the RSSI register.

3. Apply no RF input signal, and write VGA3 register with increasing VGA_SETTING value until the RSSI

floor around 6 dB above the ADC noise floor.

4. Apply an RF signal with strength equal the desired carrier sense threshold. The RF signal should

preferably be modulated with correct Baud rate and deviation. Read the RSSI register value, subtract

8, and write to CS_LEVEL in the VGA4 register. Vary the RF signal level slightly and check that carrier

sense indication (bit 3 in STATUS register) switches at the desired input level.

5. If desired, adjust the VGA_UP and VGA_DOWN settings according to the explanation in Figure 5-17.

6. Enable AGC and select LNA2 gain change level. Write 55h to VGA2 register if the resulting

VGA_SETTING>10. Otherwise, write 45h to VGA2. Modify AGC_AVG in the above VGA2 value if

faster carrier sense and AGC settling is desired.

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CC1021-RTR1 Datasheet(PDF) 34 Page - Texas Instruments

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