CC1021-RTR1 datasheet(52/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

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The AGC has a certain time-constant determined by FILTER_CLK, which depends on the IF filter

bandwidth. There is a lower limit on FILTER_CLK and hence the AGC time constant. For low data rates

the minimum time constant is too fast and the AGC will increase the gain when a "0" is received and

decrease the gain when a "1" is received. For this reason, the minimum data rate in OOK is 9.6 kBaud.

Typical figures for the receiver sensitivity (BER = 10−3) are shown in Table 5-14 for OOK.

Figure 5-29. OOK Eye Diagram, 9.6 kBaud

Table 5-14. Typical Receiver Sensitivity as a Function

of Data Rate at 433 and 868 MHz, OOK Modulation,

BER = 10–3, Pseudo-random Data (PN9 Sequence)

SENSITIVITY [dBm]

DATA

FILTER BW

433 MHz

868 MHz

RATE

[kHz]

MANCHESTER

[kBaud]

MODE

9.6

38.4

–103

–104

19.2

51.2

–102

–101

38.4

102.4

–95

–97

76.8

153.6

–92

–94

153.6

307.2

–81

–87

5.16 Crystal Oscillator

The recommended crystal frequency is 14.7456 MHz, but any crystal frequency in the range 4 to 20 MHz

can be used. Using a crystal frequency different from 14.7456 MHz might in some applications give

degraded performance. Refer to Application Note AN022 Crystal Frequency Selection (SWRA070) for

more details on the use of other crystal frequencies than 14.7456 MHz. The crystal frequency is used as

reference for the data rate (as well as other internal functions) and in the 4 to 20 MHz range the

frequencies 4.9152, 7.3728, 9.8304, 12.2880, 14.7456, 17.2032, 19.6608 MHz will give accurate data

rates as shown in Table 5-4 and an IF frequency of 307.2 kHz. The crystal frequency will influence the

programming of the CLOCK_A, CLOCK_B and MODEM registers.

An external clock signal or the internal crystal oscillator can be used as main frequency reference. An

external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The

XOSC_BYPASS bit in the INTERFACE register should be set to ‘1’ when an external digital rail-to-rail

clock signal is used. No DC block should be used then. A sine with smaller amplitude can also be used. A

DC blocking capacitor must then be used (10 nF) and the XOSC_BYPASS bit in the INTERFACE register

should be set to ‘0’. For input signal amplitude, see Section 4.8.

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