CC1021-RTR1 datasheet(68/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

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Table 5-35. VGA1 Register (11h)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

VGA1[7:6]

CS_SET[1:0]

—

Sets the number of consecutive samples at or above carrier sense

level before carrier sense is indicated (for example, on LOCK pin)

0: Set carrier sense after first sample at or above carrier sense

level

1: Set carrier sense after second sample at or above carrier sense

level

2: Set carrier sense after third sample at or above carrier sense

level

3: Set carrier sense after fourth sample at or above carrier sense

level

Increasing CS_SET reduces the number of “false” carrier sense events

due to noise at the expense of increased carrier sense response time.

VGA1[5]

CS_RESET

—

Sets the number of consecutive samples below carrier sense level

before carrier sense indication (for example, on lock pin) is reset

0: Carrier sense is reset after first sample below carrier sense level

1: Carrier sense is reset after second sample below carrier sense

level

Recommended setting: CS_RESET=1 in order to reduce the chance of

losing carrier sense due to noise.

VGA1[4:2]

VGA_WAIT[2:0]

—

Controls how long AGC, bit synchronization, AFC and RSSI levels are

frozen after VGA gain is changed when frequency is changed between

A and B or PLL has been out of lock or after RX power up

0: Freeze operation for 16 filter clocks, 8 / (filter BW) seconds

1: Freeze operation for 20 filter clocks, 10 / (filter BW) seconds

2: Freeze operation for 24 filter clocks, 12 / (filter BW) seconds

3: Freeze operation for 28 filter clocks, 14 / (filter BW) seconds

4: Freeze operation for 32 filter clocks, 16 / (filter BW) seconds

5: Freeze operation for 40 filter clocks, 20 / (filter BW) seconds

6: Freeze operation for 48 filter clocks, 24 / (filter BW) seconds

7: Freeze present levels unconditionally

VGA1[1:0]

VGA_FREEZE[1:0]

—

Controls the additional time AGC, bit synchronization, AFC and RSSI

levels are frozen when frequency is changed between A and B or PLL

has been out of lock or after RX power up

0: Freeze levels for approx. 16 ADC_CLK periods (13 µs)

1: Freeze levels for approx. 32 ADC_CLK periods (26 µs)

2: Freeze levels for approx. 64 ADC_CLK periods (52 µs)

3: Freeze levels for approx. 128 ADC_CLK periods (104 µs)

Table 5-36. VGA2 Register (12h)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

VGA2[7]

LNA2_MIN

—

Minimum LNA2 setting used in VGA

0: Minimum LNA2 gain

1: Medium LNA2 gain

Recommended setting: LNA2_MIN=0 for best selectivity.

VGA2[6]

LNA2_MAX

—

Maximum LNA2 setting used in VGA

0: Medium LNA2 gain

1: Maximum LNA2 gain

Recommended setting: LNA2_MAX=1 for best sensitivity.

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