CC1021-RTR1 datasheet(55/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

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SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

5.18 Interrupt on Pin DCLK

5.18.1 Interrupt Upon PLL Lock

In synchronous mode the DCLK pin on CC1021 can be used to give an interrupt signal to wake the

microcontroller when the PLL is locked.

PD_MODE[1:0] in the MAIN register should be set to 01. If DCLK_LOCK in the INTERFACE register is set

to 1 the DCLK signal is always logic high if the PLL is not in lock. When the PLL locks to the desired

frequency the DCLK signal changes to logic 0. When this interrupt has been detected write

PD_MODE[1:0] = 00. This will enable the DCLK signal.

This function can be used to wait for the PLL to be locked before the PA is ramped up in transmit mode. In

receive mode, it can be used to wait until the PLL is locked before searching for preamble.

5.18.2 Interrupt Upon Received Signal Carrier Sense

In synchronous mode the DCLK pin on CC1021 can also be used to give an interrupt signal to the

microcontroller when the RSSI level exceeds a certain threshold (carrier sense threshold). This function

can be used to wake or interrupt the microcontroller when a strong signal is received.

Gating the DCLK signal with the carrier sense signal makes the interrupt signal.

This function should only be used in receive mode and is enabled by setting DCLK_CS = 1 in the

INTERFACE register.

The DCLK signal is always logic high unless carrier sense is indicated. When carrier sense is indicated

the DCLK starts running. When gating the DCLK signal with the carrier sense signal at least 2 dummy bits

should be added after the data payload in TX mode. The reason being that the carrier sense signal is

generated earlier in the receive chain (that is, before the demodulator), causing it to be updated 2 bits

before the corresponding data is available on the DIO pin.

In transmit mode DCLK_CS must be set to 0. Refer to CC1021 Errata Note 001, located in the CC1021

product folder.

5.19 PA_EN and LNA_EN Digital Output Pins

5.19.1 Interfacing an External LNA or PA

CC1021 has two digital output pins, PA_EN and LNA_EN, which can be used to control an external LNA

or PA. The functionality of these pins are controlled through the INTERFACE register. The outputs can

also be used as general digital output control signals.

EXT_PA_POL and EXT_LNA_POL control the active polarity of the signals.

EXT_PA and EXT_LNA control the function of the pins. If EXT_PA = 1, then the PA_EN pin will be

activated when the internal PA is turned on. Otherwise, the EXT_PA_POL bit controls the PA_EN pin

directly. If EXT_LNA = 1, then the LNA_EN pin will be activated when the internal LNA is turned on.

Otherwise, the EXT_LNA_POL bit controls the LNA_EN pin directly.

These two pins can therefore also be used as two general control signals, Section 5.19.2. In the TI

reference design, LNA_EN and PA_EN are used to control the external T/R switch.

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CC1021-RTR1 Datasheet(PDF) 55 Page - Texas Instruments

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