CC1021-RTR1 datasheet(67/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

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SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

Table 5-33. AFC_CONTROL Register (0Fh)(1)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

AFC_CONTROL[7:6]

SETTLING[1:0]

—

Controls AFC settling time versus accuracy

0: AFC off; zero average frequency is used in demodulator

1: Fastest settling; frequency averaged over 1 0/1 bit pair

2: Medium settling; frequency averaged over 2 0/1 bit pairs

3: Slowest settling; frequency averaged over 4 0/1 bit pairs

Recommended setting:

AFC_CONTROL=3 for higher accuracy unless it is essential to

have the fastest settling time when transmission starts after RX

is activated.

AFC_CONTROL[5:4]

RXDEV_X[1:0]

—

RX frequency deviation exponent

AFC_CONTROL[3:0]

RXDEV_M[3:0]

—

RX frequency deviation mantissa

Expected RX deviation should be:

Baud rate × RXDEV_M × 2(RXDEV_X−3) / 3

To find RXDEV_M given the deviation and RXDEV_X:

RXDEV_M = 3 × deviation × 2(3−RXDEV_X) / Baud rate

Decrease RXDEV_X and try again if RXDEV_M < 8.

Increase RXDEV_X and try again if RXDEV_M

≥ 16.

(1)

The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100 kBaud data rate and below. The RX

frequency deviation should be close to the TX frequency deviation for FSK and for GFSK at 100 kBaud data rate and above.

Table 5-34. FILTER Register (10h)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

FILTER[7]

FILTER_BYPASS

Bypass analog image rejection / anti-alias filter. Set to 1 for increased

dynamic range at high Baud rates.

Recommended setting:

FILTER_BYPASS=0 below 76.8 kBaud,

FILTER_BYPASS=1 for 76.8 kBaud and up.

FILTER[6:5]

DEC_SHIFT[1:0]

—

Number of extra bits to shift decimator input (may improve filter

accuracy and lower power consumption).

Recommended settings:

DEC_SHIFT=0 when DEC_DIV

≤ 1

(receiver channel bandwidth

≥ 153.6 kHz),

DEC_SHIFT=1 when DEC_DIV > 1

(receiver channel bandwidth < 153.6 kHz)

FILTER[4:3]

—

Reserved

FILTER[2:0]

DEC_DIV[2:0]

—

Decimation clock divisor

0: Decimation clock divisor = 1, 307.2 kHz channel filter BW.

1: Decimation clock divisor = 2, 153.6 kHz channel filter BW.

…

6: Decimation clock divisor = 7, 43.9 kHz channel filter BW.

31: Decimation clock divisor = 8, 38.4 kHz channel filter BW.

Channel filter bandwidth is 307.2 kHz divided by the decimation clock

divisor.

Detailed Description

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