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CC1021-RTR1 Datasheet(PDF) 20 Page - Texas Instruments |
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CC1021-RTR1 Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 91 page  PCLK PDI PSEL Address Read mode 6 5 4 3 2 1 0 T SS T CL,min T CH,min T HS R PDO 7 6 5 4 3 2 1 0 Data byte T SH Not Recommended for New Designs NRND CC1021 SWRS045D – JANUARY 2006 – REVISED JANUARY 2015 www.ti.com Figure 5-5. Configuration Registers Read Operation Table 5-1. Serial Interface, Timing Specification(1) PARAMETER MIN MAX UNIT CONDITIONS FPCLK PCLK, clock frequency 10 MHz TCL,min PCLK low pulse duration 50 ns The minimum time PCLK must be low. TCH,min PCLK high pulse duration 50 ns The minimum time PCLK must be high. The minimum time PSEL must be low before positive TSS PSEL setup time 25 ns edge of PCLK. The minimum time PSEL must be held low after the THS PSEL hold time 25 ns negative edge of PCLK. TSH PSEL high time 50 ns The minimum time PSEL must be high. The minimum time data on PDI must be ready before the TSD PDI setup time 25 ns positive edge of PCLK. The minimum time data must be held at PDI, after the THD PDI hold time 25 ns positive edge of PCLK. Trise Rise time 100 ns The maximum rise time for PCLK and PSEL Tfall Fall time 100 ns The maximum fall time for PCLK and PSEL (1) The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is valid for is 20 pF. 5.6 Signal Interface The CC1021 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase- level) encoded data. CC1021 can also synchronize the data from the demodulator and provide the data clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register. CC1021 can be configured for three different data formats: • Synchronous NRZ mode • Transparent Asynchronous UART mode • Synchronous Manchester encoded mode 20 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1021 |
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