CC1021-RTR1 datasheet(46/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

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The combined charge pump and phase detector gain (in A/rad) is given by the charge pump current

divided by 2

π.

The PLL bandwidth will limit the maximum modulation frequency and hence, data rate.

5.12.2 VCO and PLL Self-Calibration

To compensate for supply voltage, temperature and process variations, the VCO and PLL must be

calibrated. The calibration is performed automatically and sets the maximum VCO tuning range and

optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the

self-calibration can be initiated by setting the CAL_START bit in the CALIBRATE register. The calibration

result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage

drops (typically more than 0.25 V) or temperature variations (typically more than 40°C) occur after

calibration, a new calibration should be performed.

The nominal VCO control voltage is set by the CAL_ITERATE[2:0] bits in the CALIBRATE register.

The CAL_COMPLETE bit in the STATUS register indicates that calibration has finished. The calibration

wait time (CAL_WAIT) is programmable and is proportional to the internal PLL reference frequency. The

highest possible reference frequency should be used to get the minimum calibration time. It is

recommended to use CAL_WAIT[1:0] = 11 in order to get the most accurate loop bandwidth.

Table 5-11. Typical Calibration Times

CALIBRATION

REFERENCE FREQUENCY [MHz]

TIME [MS]

CAL_WAIT

1.8432

7.3728

9.8304

49 ms

12 ms

10 ms

60 ms

15 ms

11 ms

71 ms

18 ms

13 ms

109 ms

27 ms

20 ms

The CAL_COMPLETE bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0] =

0101, and used as an interrupt input to the microcontroller.

To check that the PLL is in lock the user should monitor the LOCK_CONTINUOUS bit in the STATUS

LOCK_SELECT[3:0] = 0010.

There are separate calibration values for the two frequency registers. However, dual calibration is possible

if all of the following conditions apply:

•

The two frequencies A and B differ by less than 1 MHz.

•

Reference frequencies are equal (REF_DIV_A[2:0] = REF_DIV_B[2:0] in the CLOCK_A/CLOCK_B

registers).

•

VCO currents are equal (VCO_CURRENT_A[3:0] = VCO_CURRENT_B[3:0] in the VCO register).

The CAL_DUAL bit in the CALIBRATE register controls dual or separate calibration.

The single calibration algorithm (CAL_DUAL=0) using separate calibration for RX and TX frequency is

illustrated in Figure 5-26. The same algorithm is applicable for dual calibration if CAL_DUAL=1. Refer to

Application Note AN023 CC1020 MCU Interfacing (SWRA069), which includes example source code for

single calibration.

TI recommends that single calibration be used for more robust operation.

There is a finite possibility that the PLL self-calibration will fail. The calibration routine in the source code

should include a loop so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock

the first time. Refer to CC1021 Errata Note 002, available in the CC1021 product folder.

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