CC1021-RTR1 datasheet(75/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

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SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

Table 5-52. TEST2 Register (22h, for Test Only)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

TEST2[7]

BREAK_LOOP

0: PLL loop closed

1: PLL loop open

TEST2[6]

CHP_OVERRIDE

0: use calibrated value

1: use CHP_CO[3:0] value

TEST2[5]

VCO_OVERRIDE

0: use calibrated value

1: use VCO_AO[4:0] value

TEST2[4:0]

VCO_AO[4:0]

—

VCO_ARRAY override value

Table 5-53. TEST3 Register (23h, for Test Only)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

TEST3[7]

VCO_CAL_MANUAL

Enables “manual” VCO calibration (test only)

TEST3[6]

VCO_CAL_OVERRIDE

Override VCO current calibration

0: Use calibrated value

1: Use VCO_CO[5:0] value

VCO_CAL_OVERRIDE controls VCO_CAL_CLK

if VCO_CAL_MANUAL=1. Negative transitions are then used to

sample VCO_CAL_COMP.

TEST3[5:0]

VCO_CO[5:0]

—

VCO_CAL_CURRENT override value

Table 5-54. TEST4 Register (24h, for Test Only)(1)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

TEST4[7]

CHP_DISABLE

Disable normal charge pump operation

TEST4[6]

CHP_TEST_UP

Force charge pump to output “up” current

TEST4[5]

CHP_TEST_DN

Force charge pump to output “down” current

TEST4[4:3]

TM_IQ[1:0]

—

Value of differential I and Q outputs from mixer when TM_ENABLE=1

0: I output negative, Q output negative

1: I output negative, Q output positive

2: I output positive, Q output negative

3: I output positive, Q output positive

TEST4[2]

TM_ENABLE

Enable DC control of mixer output (for testing)

TEST4[1]

TF_ENABLE

Connect analog test module to filter inputs

TEST4[0]

TA_ENABLE

Connect analog test module to ADC inputs

(1)

If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD,

INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2]=1.

Table 5-55. TEST5 Register (25h, for Test Only)

DEFAULT

NAME

ACTIVE

DESCRIPTION

VALUE

TEST5[7]

F_COMP_ENABLE

Enable frequency comparator output F_COMP from phase detector

TEST5[6]

SET_DITHER_CLOCK

Enable dithering of delta-sigma clock

TEST5[5]

ADC_TEST_OUT

Outputs ADC samples on LOCK and DIO, while ADC_CLK is output

on DCLK

TEST5[4]

CHOP_DISABLE

Disable chopping in ADC integrators

TEST5[3]

SHAPING_DISABLE

Disable ADC feedback mismatch shaping

TEST5[2]

VCM_ROT_DISABLE

Disable rotation for VCM mismatch shaping

Detailed Description

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