CC1021-RTR1 datasheet(13/91 Pages) TI1

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Not Recommended for New Designs NRND

CC1021

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SWRS045D – JANUARY 2006 – REVISED JANUARY 2015

4.9

Frequency Synthesizer

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical

specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V, fC = 14.7456

MHz if nothing else stated.

PARAMETER

TYP

UNIT

CONDITION

At 12.5 kHz offset from carrier

–79

dBc/Hz

Unmodulated carrier

At 25 kHz offset from carrier

–80

dBc/Hz

Measured using loop filter

Phase noise, 402 to 470 MHz

At 50 kHz offset from carrier

–87

dBc/Hz

components given in Table 6-2. The

phase noise will be higher for larger

At 100 kHz offset from carrier

–100

dBc/Hz

PLL loop filter bandwidth.

At 1 MHz offset from carrier

–105

dBc/Hz

At 12.5 kHz offset from carrier

–73

dBc/Hz

Unmodulated carrier

At 25 kHz offset from carrier

–74

dBc/Hz

Measured using loop filter

Phase noise, 804 to 960 MHz

At 50 kHz offset from carrier

–81

dBc/Hz

components given in Table 6-2. The

phase noise will be higher for larger

At 100 kHz offset from carrier

–94

dBc/Hz

PLL loop filter bandwidth.

At 1 MHz offset from carrier

–111

dBc/Hz

Loop filter 2, up to 19.2 kBaud

kHz

After PLL and VCO calibration.

The PLL loop bandwidth is

PLL loop filter bandwidth

programmable.

Loop filter 3, up to 38.4 kBaud

30.5

kHz

See Table 5-12 for loop filter

component values.

Loop filter 2, up to 19.2 kBaud

140

µs

307.2 kHz frequency step to RF

frequency within ±10 kHz, ±15 kHz,

Loop filter 3, up to 38.4 kBaud

µs

±50 kHz settling accuracy for loop

PLL lock time (RX / TX turn

filter 2, 3 and 5 respectively.

time)

Depends on loop filter component

Loop filter 5, up to 153.6 kBaud

µs

values and PLL_BW register

setting. See Table 5-13 for more

details.

Loop filter 2, up to 19.2 kBaud

1300

µs

Time from writing to registers to RF

frequency within ±10 kHz, ±15 kHz,

Loop filter 3, up to 38.4 kBaud

1080

µs

±50 kHz settling accuracy for loop

PLL turn-on time.

filter 2, 3 and 5 respectively.

From power down mode with

Depends on loop filter component

crystal oscillator running.

Loop filter 5, up to 153.6 kBaud

700

µs

values and PLL_BW register

setting. See Table 5-12 for more

details.

4.10 Digital Inputs / Outputs

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical

specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V, fC = 14.7456

MHz if nothing else stated.

PARAMETER

MIN

TYP

MAX

UNIT

CONDITION

Logic "0" input voltage

0.3 × VDD

Logic "1" input voltage

0.7 × VDD

VDD

Output current –2.0 mA,

Logic "0" output voltage

0.4

3.0 V supply voltage

Output current 2.0 mA,

Logic "1" output voltage

2.5

VDD

3.0 V supply voltage

Input signal equals GND.

PSEL has an internal pullup

Logic "0" input current

N/A

–1

µA

resistor and during

configuration the current

will be –350 mA.

Logic "1" input current

N/A

µA

Input signal equals VDD

TX mode, minimum time

DIO must be ready before

DIO setup time

the positive edge of DCLK.

Data should be set up on

the negative edge of DCLK.

Specifications

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