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RZ/T1 Datasheet(PDF) 117 Page - Renesas Technology Corp |
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RZ/T1 Datasheet(HTML) 117 Page - Renesas Technology Corp |
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117 / 139 page ![]() R01DS0228EJ0200 Rev.2.00 Page 117 of 139 Jun. 30, 2025 RZ/T1 Group 2. Electrical Characteristics 2.4.5.14 ETHERC Timing Note 1. ETHn_TXEN, ETHn_TXD1, ETHn_TXD0 Note 2. ETHn_RXDV, ETHn_RXD1, ETHn_RXD0, ETHn_RXER n = 0 to 2 Table 2.32 ETHERC Timing Output load conditions: VOH = 2.0 V, VOL1 = 0.8 V, C = 25 pF (RMII) VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF (MII) Item Symbol min max Unit Test Conditions ETHERC (RMII) CLKOUT25Mn cycle time Tck 20 ― ns Figure 2.70 to Figure 2.73 ETHn_Txxx*1 output delay time Tco 2 16 ns ETHn_Rxxx*2 setup time Tsu 4― ns ETHn_Rxxx*2 hold time Thd 2― ns ETHn_xxxx*1, *2 rising/falling time Tr, Tf 0.5 5 ns ETHERC (MII) ETHn_TXC cycle time tTcyc 40 ― ns ― ETHn_TXEN output delay time tTENd 0 25 ns Figure 2.74 ETHn_TXD0 to ETHn_TXD3 output delay time tMTDd 025 ns ETHn_TXER output delay time tTERd ― 25 ns Figure 2.75 ETHn_RXC cycle time tTRcyc 40 ― ns ― ETHn_RXDV setup time tRDVs 10 ― ns Figure 2.76 ETHn_RXDV hold time tRDVh 10 ― ns ETHn_RXD0 to ETHn_RXD3 setup time tMRDs 10 ― ns ETHn_RXD0 to ETHn_RXD3 hold time tMRDh 10 ― ns ETHn_RXER setup time tRERs 10 ― ns Figure 2.77 ETHn_RXER hold time tRERh 10 ― ns Note 1. ETHn_TXEN, ETHn_TXD1, ETHn_TXD0 Note 2. ETHn_RXDV, ETHn_RXD1, ETHn_RXD0, ETHn_RXER Figure 2.70 Timing with the CLKOUT25Mn and RMII Signals Tck Tco CLKOUT25Mn (50MHz REFCLK) ETHn_Txxx*1 50% 0.8V Tr Tf ETHn_Rxxx *2 2.4V 0.8V Tsu Thd Signal Signal Signal Signal 0.8V 0.8V 2.0V 2.0V 2.0V 0.8V 2.4V Change in signal level Change in signal level Change in signal level Change in signal level Change in signal level Change in signal level |
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