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RZ/T1 Datasheet(PDF) 114 Page - Renesas Technology Corp |
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RZ/T1 Datasheet(HTML) 114 Page - Renesas Technology Corp |
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114 / 139 page  R01DS0228EJ0200 Rev.2.00 Page 114 of 139 Jun. 30, 2025 RZ/T1 Group 2. Electrical Characteristics 2.4.5.12 Serial Sound Interface Timing Table 2.30 Serial Sound Interface Timing Output load conditions: VOH = VCCQ33 × 0.5, VOL1 = VCCQ33 × 0.5, C = 30 pF Item Symbol Min. Max. Unit Test Conditions SSI AUDIO_CLK input frequency tAUDIO 150 MHz Output clock cycle tO 150 64000 ns Figure 2.65 Input clock cycle tI 150 64000 ns Clock high level tHC 60 ― ns Clock low level tLC 60 ― ns Clock rising time tRC ―25 ns Data delay time tDTR -5 25 ns Figure 2.66, Figure 2.67 Setup time tSR 25 ― ns Hold time tHTR 25 ― ns WS change edge SSITXD0 output delay TDTRW ― 25 ns Figure 2.68 Figure 2.65 Clock Input/Output Timing Figure 2.66 Transmit/Receive Timing (SSISCK0 Rising Synchronous) SSISCK0 tHC tLC tRC tI, tO tSR tHTR tDTR SSISCK0 (input or output) SSIWS0, SSIRXD0 (input) SSIWS0, SSITXD0 (output) |
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