AMD-K6-2ESLASH400AMZ datasheet(27/332 Pages) AMD

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Chapter 2

Internal Architecture

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Figure 1. AMD-K6™-2E Processor Block Diagram

Decoders

Decoding of the x86 instructions begins when the on-chip

instruction cache is filled. Predecode logic determines the

length of an x86 instruction on a byte-by-byte basis. This

pre d ec o d e info r m a t io n i s st ored, al ong wit h t h e x 8 6

instructions, in the instruction cache, to be used later by the

decoders. The decoders translate on-the-fly, with no additional

latency, up to two x86 instructions per clock into RISC86

operations.

Note: In this chapter, “clock” refers to a processor clock.

The AMD-K6-2E processor categorizes x86 instructions into

three types of decodes—short, long, and vector. The decoders

process either two short, one long, or one vector decode at a

time.

Store

Unit

Branch

Unit

Store

Queue

Instruction

Control Unit

Scheduler

Buffer

(24 RISC86)

Six RISC86 ®

Operation Issue

Four RISC86

Decode

Out-of-Order

Execution Engine

32-KByte Level-One Dual-Port Data Cache

128-Entry DTLB

20-KByte Predecode Cache

64-Entry ITLB

Multiple Instruction Decoders

x86 to RISC86

Branch Logic

(8192-Entry BHT)

(16-Entry BTC)

(16-Entry RAS)

16-Byte Fetch

Load

Unit

Predecode

Logic

Level-One Cache

Controller

FPU

32-KByte Level-One Instruction Cache

Integer/

Multimedia /3DNow!

100 MHz

Super7

Bus

Interface

Integer/

Multimedia/3DNow!

AMD-K6-2E/400AMZ Datasheet(PDF) 27 Page - Advanced Micro Devices

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