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AMD-K6-2E/400AMZ Datasheet(PDF) 61 Page - Advanced Micro Devices

No. de pieza AMD-K6-2E/400AMZ
Descripción Electrónicos  AMD-K6??2E Embedded Processor
PDF  332 Pages
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Fabricante Electrónico  AMD [Advanced Micro Devices]
Página de inicio  http://www.amd.com
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AMD-K6-2E/400AMZ Datasheet(HTML) 61 Page - Advanced Micro Devices

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Chapter 3
Software Environment
43
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Preliminary Information
Extended Feature
Enable Register
(EFER)
The extended feature enable register (EFER) contains the
contro l bits that enab le the ex tended features of th e
AMD-K6-2E processor. Figure 34 shows the format of the EFER
register, and Table 6 defines the function of each bit in the
EFER register.
Figure 34. Extended Feature Enable Register (EFER)
For more information about the EWBEC bits, see “EWBE#
Control” on page 205.
Table 6. Extended Feature Enable Register (EFER)Definition
Bit
Description
R/W Function
63–4
Reserved
R
Writing a 1 to any reserved bit causes a general protection fault to occur. All
reserved bits are always read as 0.
3-2
EWBE# Control
(EWBEC)
R/W
This 2-bit field controls the behavior of the processor with respect to the ordering of
write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE# Disable
(GEWBED) and Speculative EWBE# Disable (SEWBED), respectively.
1
Data Prefetch Enable
(DPE)
R/W
DPE must be set to 1 to enable data prefetching (this is the default setting following
reset). If enabled, cache misses initiated by a memory read within a 32-byte cache
line are conditionally followed by cache-line fetches of the other line in the 64-byte
sector.
0
System Call Extension
(SCE)
R/W
SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions.
10
63
S
C
E
2
3
4
D
P
E
EWBEC
Symbol
Description
Bit
EWBEC
EWBE# Control
3-2
DPE
Data Prefetch Enable
1
SCE
System Call Extension
0
Reserved



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