AMD-K6-2ESLASH400AMZ datasheet(13/332 Pages) AMD

13 / 332 page

List of Tables

xiii

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

List of Tables

Table 1.

Execution Latency and Throughput of Execution Units .19

Table 2.

General-Purpose Registers .................................................24

Table 3.

General-Purpose Register Doubleword, Word,

and Byte Names....................................................................25

Table 4.

Segment Registers ...............................................................26

Table 5.

AMD-K6™-2E Processor Model 8/[F:8]

Model-Specific Registers.....................................................40

Table 6.

Extended Feature Enable Register (EFER) Definition ...43

Table 7.

SYSCALL/SYSRET Target Address Register

(STAR) Definition ................................................................44

Table 8.

Memory Management Registers.........................................47

Table 9.

Application Segment Types ................................................53

Table 10. System Segment and Gate Types .......................................54

Table 11. Summary of Exceptions and Interrupts.............................55

Table 12. Integer Instructions .............................................................57

Table 13. Floating-Point Instructions .................................................74

Table 14. MMX™ Instructions.............................................................78

Table 15. 3DNow!™ Instructions.........................................................81

Table 16. Processor-to-Bus Clock Ratios ............................................93

Table 17. Output Pin Float Conditions .............................................127

Table 18. Input Pin Types ..................................................................130

Table 19. Output Pin Float Conditions .............................................131

Table 20. Input/Output Pin Float Conditions ..................................131

Table 21. Test Pins..............................................................................131

Table 22. Bus Cycle Definition ..........................................................132

Table 23. Special Cycles.....................................................................132

Table 24. Bus-Cycle Order During Misaligned Memory Transfers . 140

Table 25. A[4:3] Address-Generation Sequence During Bursts .....142

Table 26. Bus-Cycle Order During Misaligned I/O Transfers .........147

Table 27. Interrupt Acknowledge Operation Definition ................168

Table 28. Encodings for Special Bus Cycles.....................................170

Table 29. Output Signal State After RESET....................................180

Table 30. Register State After RESET .............................................181

Table 31. PWT Signal Generation .....................................................188

Table 32. PCD Signal Generation .....................................................189

Table 33. CACHE# Signal Generation..............................................189

Table 34. Data Cache States for Read and Write Accesses............198

Table 35. Cache States for Inquire Cycles, Snoops, Flushes,

and Invalidation .................................................................202

Table 36. Snoop Action ......................................................................203

Table 37. EWBEC Settings.................................................................207

Table 38. WC/UC Memory Type ........................................................209

Table 39. Valid Masks and Range Sizes ...........................................210

Table 40. Initial State of Registers in System Management Mode . 219

Table 41. SMM State-Save Area Map ...............................................219

AMD-K6-2E/400AMZ Datasheet(PDF) 13 Page - Advanced Micro Devices

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