AMD-K6-2ESLASH400AMZ datasheet(9/332 Pages) AMD

9 / 332 page

List of Figures

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

List of Figures

Figure 1.

AMD-K6™-2E Processor Block Diagram.........................9

Figure 2.

Cache Sector Organization .............................................12

Figure 3.

The Instruction Buffer ....................................................14

Figure 4.

AMD-K6™-2E Processor Decode Logic .........................15

Figure 5.

AMD-K6™-2E Processor Scheduler...............................18

Figure 6.

Figure 7.

EAX Register with 16-Bit and 8-Bit

Name Components ..........................................................24

Figure 8.

Integer Data Registers....................................................25

Figure 9.

Segment Register ............................................................26

Figure 10.

Segment Usage ................................................................27

Figure 11.

Floating-Point Register...................................................28

Figure 12.

FPU Status Word Register .............................................28

Figure 13.

FPU Control Word Register ...........................................29

Figure 14.

FPU Tag Word Register..................................................29

Figure 15.

Packed Decimal Data Register ......................................30

Figure 16.

Precision Real Data Registers .......................................30

Figure 17.

MMX™/3DNow!™ Registers ..........................................31

Figure 18.

MMX™ Data Types .........................................................32

Figure 19.

3DNow!™ Data Types .....................................................33

Figure 20.

EFLAGS Register ............................................................34

Figure 21.

Control Register 4 (CR4) ................................................35

Figure 22.

Control Register 3 (CR3) ................................................35

Figure 23.

Control Register 2 (CR2) ................................................35

Figure 24.

Control Register 1 (CR1) ................................................36

Figure 25.

Control Register 0 (CR0) ................................................36

Figure 26.

Debug Register DR7 .......................................................37

Figure 27.

Debug Register DR6 .......................................................38

Figure 28.

Debug Registers DR5 and DR4......................................38

Figure 29.

Debug Registers DR3, DR2, DR1, and DR0..................39

Figure 30.

Machine-Check Address Register (MCAR) ..................41

Figure 31.

Machine-Check Type Register (MCTR) ........................41

Figure 32.

Test Register 12 (TR12)..................................................42

Figure 33.

Time Stamp Counter (TSC) ............................................42

Figure 34.

Extended Feature Enable Register (EFER).................43

Figure 35.

SYSCALL/SYSRET Target Address

Figure 36.

Write Handling Control Register (WHCR)...................44

Figure 37.

UC/WC Cacheability Control Register (UWCCR) .......45

Figure 38.

Processor State Observability Register (PSOR) ..........45

Figure 39.

Page Flush/Invalidate Register (PFIR).........................46

Figure 40.

Memory Management Registers ....................................47

Figure 41.

Task State Segment (TSS) ..............................................48

Figure 42.

4-Kbyte Paging Mechanism ............................................49

Figure 43.

4-Mbyte Paging Mechanism ...........................................50

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