AMD-K6-2ESLASH400AMZ datasheet(10/332 Pages) AMD

10 / 332 page

List of Figures

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

Figure 44.

Page Directory Entry 4-Kbyte Page Table (PDE) ........51

Figure 45.

Page Directory Entry 4-Mbyte Page Table (PDE) .......51

Figure 46.

Page Table Entry (PTE)..................................................52

Figure 47.

Application Segment Descriptor ...................................53

Figure 48.

System Segment Descriptor ...........................................54

Figure 49.

Gate Descriptor ...............................................................55

Figure 50.

Waveform Definitions...................................................134

Figure 51.

Bus State Machine Diagram .........................................135

Figure 52.

Non-Pipelined Single-Transfer Memory

Read/Write and Write Delayed by EWBE# ................139

Figure 53.

Misaligned Single-Transfer Memory

Read and Write..............................................................141

Figure 54.

Burst Reads and Pipelined Burst Reads .....................143

Figure 55.

Burst Writeback due to Cache-Line Replacement.....145

Figure 56.

Basic I/O Read and Write .............................................146

Figure 57.

Misaligned I/O Transfer................................................147

Figure 58.

Basic HOLD/HLDA Operation .....................................149

Figure 59.

HOLD-Initiated Inquire Hit to Shared

or Exclusive Line...........................................................151

Figure 60.

HOLD-Initiated Inquire Hit to Modified Line............153

Figure 61.

AHOLD-Initiated Inquire Miss ....................................155

Figure 62.

AHOLD-Initiated Inquire Hit to Shared

or Exclusive Line...........................................................157

Figure 63.

AHOLD-Initiated Inquire Hit to Modified Line.........159

Figure 64.

AHOLD Restriction.......................................................161

Figure 65.

BOFF# Timing................................................................163

Figure 66.

Basic Locked Operation................................................165

Figure 67.

Locked Operation with BOFF# Intervention..............167

Figure 68.

Interrupt Acknowledge Operation ..............................169

Figure 69.

Basic Special Bus Cycle (Halt Cycle) ..........................171

Figure 70.

Shutdown Cycle .............................................................172

Figure 71.

Stop Grant and Stop Clock Modes, Part 1 ..................174

Figure 72.

Stop Grant and Stop Clock Modes, Part 2 ..................175

Figure 73.

INIT-Initiated Transition from Protected Mode

to Real Mode..................................................................177

Figure 74.

Cache Organization .......................................................185

Figure 75.

Cache Sector Organization ...........................................186

Figure 76.

Write Handling Control Register (WHCR).................194

Figure 77.

Write Allocate Logic Mechanisms and Conditions ....195

Figure 78.

Page Flush/Invalidate Register (PFIR).......................200

Figure 79.

UC/WC Cacheability Control Register (UWCCR) .....208

Figure 80.

External Logic for Supporting Floating-Point

Exceptions......................................................................215

Figure 81.

SMM Memory.................................................................218

Figure 82.

TAP State Diagram .......................................................237

Figure 83.

Debug Register DR7 .....................................................241

Figure 84.

Debug Register DR6 .....................................................242

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