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AMD-K6-2E/400AMZ Datasheet(PDF) 60 Page - Advanced Micro Devices |
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AMD-K6-2E/400AMZ Datasheet(HTML) 60 Page - Advanced Micro Devices |
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60 / 332 page ![]() 42 Software Environment Chapter 3 AMD-K6™-2E Processor Data Sheet 22529B/0—January 2000 Preliminary Information Test Register 12 (TR12) Test register 12 provides a method for disabling the L1 caches. Figure 32 shows the format of the TR12 register. Figure 32. Test Register 12 (TR12) Time Stamp Counter With each processor clock cycle, the processor increments the 64-bit time stamp counter (TSC) MSR. Figure 33 shows the format of the TSC register. Figure 33. Time Stamp Counter (TSC) 42 1 0 63 C I 3 Reserved Symbol Description Bit CI Cache Inhibit Bit 3 0 63 TSC |
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