AMD-K6-2ESLASH400AMZ datasheet(62/332 Pages) AMD

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Software Environment

Chapter 3

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

SYSCALL/SYSRET

Target Address

The SYSCALL/SYSRET target address register (STAR)

contains the target EIP a ddre ss used by the SYSCALL

instruction and the 16-bit code and stack segment selector

bases used by the SYSCALL and SYSRET instructions. Figure

35 shows the format of the STAR register, and Table 7 defines

the function of each bit of the STAR register. For more

information, see the SYSCALL and SYSRET Instruction

Specification Application Note, order #21086.

Figure 35. SYSCALL/SYSRET Target Address Register (STAR)

Write Handling

Control Register

(WHCR)

The write handling control register (WHCR) is an MSR that

contains two fields—the write allocate enable limit (WAELIM)

field, and the write allocate enable 15-to-16-Mbyte (WAE15M)

bit. Figure 36 shows the format of the WHCR register. See

“Write Allocate” on page 192 for more information.

Figure 36. Write Handling Control Register (WHCR)

Target EIP Address

SYSCALL CS Selector and SS

Selector Base

SYSRET CS Selector and SS

Selector Base

Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition

Bit

Description

R/W

63–48

SYSRET CS and SS Selector Base

R/W

47–32

SYSCALL CS and SS Selector Base

R/W

31–0

Target EIP Address

R/W

WAELIM

Note: Hardware RESET initializes this MSR to all zeros.

Symbol

Description

Bits

WAELIM

Write Allocate Enable Limit

31-22

WAE15M

Write Allocate Enable 15-to-16-Mbyte 16

Reserved

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