AMD-K6-2ESLASH400AMZ datasheet(28/332 Pages) AMD

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Internal Architecture

Chapter 2

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

The three types of decodes have the following characteristics:

Short decodes—x86 instructions that are less than or equal

to seven bytes long

Long decodes—x86 instructions less than or equal to 11

bytes long

Vector decodes—complex x86 instructions

Short and long decodes are processed completely within the

decoders. Vector decodes are started by the decoders and then

completed by fetched sequences from an on-chip ROM. After

decoding, the RISC86 operations are delivered to the scheduler

for dispatching to the execution units.

Scheduler/Instruction

Control Unit

The centralized scheduler or buffer is managed by the ICU. The

ICU buffers and manages up to 24 RISC86 operations at a time.

This equals from 6 to 12 x86 instructions. This buffer size (24) is

perfectly matched to the processor’s six-stage RISC86 pipeline,

four RISC86-operations decode rate, and ten parallel execution

units.

The scheduler accepts as many as four RISC86 operations at a

time from the decod ers an d re tires up to fo ur RISC 86

ope rat ions per c l oc k c y c l e. T h e ICU is ca pa ble of

simultaneously issuing up to six RISC86 operations at a time to

the execution units. This consists of the following types of

operations:

Memory load operation

Memory store operation

Complex integer, MMX, or 3DNOW! register operation

Simple integer register operation

Floating-point register operation

Branch condition evaluation

Registers

When managing the RISC86 operations, the ICU uses 69

ph ysical

r egi st er s

c o nt ai ned

w i t h in

the

RISC 8 6

microarchitecture.

Forty-eight of the physical registers are located in a general

•

Twenty-four of these are rename registers.

•

The other twenty-four are committed or architectural

registers, consisting of 16 scratch registers and 8 registers

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