AMD-K6-2ESLASH400AMZ datasheet(29/332 Pages) AMD

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Chapter 2

Internal Architecture

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

that correspond to the x86 general-purpose registers—

EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI.

An analogous set of 21 registers is available specifically for

MMX and 3DNow! operations.

•

Twelve of these are MMX/3DNow! rename registers.

•

Nine are MMX/3DNow! committed or architectural

registers, consisting of one scratch register and eight

registers that correspond to the MMX registers (mm0–

mm7). For more detailed information, see the 3DNow!™

Technology Manual, order #21928.

Branch Logic

T h e AMD-K6 -2 E pr oce s sor i s d e sig n ed wit h h i g h l y

sophisticated dynamic branch logic consisting of the following:

Branch history/Prediction table

Branch target cache

Return address stack

The AMD-K6-2E processor implements a two-level branch

prediction scheme based on an 8192-entry branch history table.

The branch history table stores prediction information that is

used for predicting conditional branches. Because the branch

history table does not store predicted target addresses, special

address ALUs calculate target addresses on-the-fly during

instruction decode.

Th e bra n ch t a rg e t c a ch e aug m e n t s predic t e d branch

performance by avoiding a one clock cache-fetch penalty. This

specialized target cache does this by supplying the first 16 bytes

of target instructions to the decoders when branches are

predicted. The return address stack is a unique device

specifically designed for optimizing CALL and RETURN pairs.

In summary, the AMD-K6-2E processor uses dynamic branch

logic to minimize delays due to the branch instructions that are

common in x86 software.

3DNow!™ Technology

AMD has taken a lead role in improving the multimedia and 3D

capabilities of the x86 processor family with the introduction of

3DNow! technology, which uses a packed, single-precision,

floating-point data format and Single Instruction Multiple Data

(SIMD) operations also found in the MMX technology model.

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