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AMD-K6-2E/400AMZ Datasheet(PDF) 67 Page - Advanced Micro Devices |
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AMD-K6-2E/400AMZ Datasheet(HTML) 67 Page - Advanced Micro Devices |
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67 / 332 page ![]() Chapter 3 Software Environment 49 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information 3.4 Paging The AMD-K6-2E processor can physically address up to four Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the operating system design and the values set up in the page directory entries (PDE) and page table entries (PTE). The processor can access both 4-Kbyte pages and 4-Mbyte pages, and the page sizes can be intermixed within a page directory. When the page size extension (PSE) bit in CR4 is set, the processor translates linear addresses using either the 4-Kbyte translation lookaside buffer (TLB) or the 4-Mbyte TLB, depending on the state of the page size (PS) bit in the page directory entry. Figures 42 and 43 show how 4-Kbyte and 4-Mbyte page translations work. Figure 42. 4-Kbyte Paging Mechanism Linear Address Page Directory Page Table 4-Kbyte Page Frame CR3 0 11 12 21 31 22 Page Directory Offset Page Table Offset Page Offset PDE PTE Physical Address |
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