MP2884A datasheet(21/107 Pages) MPS

21 / 107 page

MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID

MP2884A Rev. 1.01

www.MonolithicPower.com

12/25/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Figure 11a: MP2884A Power-On Sequence at Regular-Power Mode

Figure 11b shows the power-on sequence of

the MP2884A in low-power mode.

t0~t1: at t0, VDD33 is supplied by a +3.3V

voltage and reaches the VDD33 UVLO_ON

threshold at t1. VDD18 reaches +1.8V when

VDD33 is greater than 1.8V.

t1~t2: after t1, VDD33 rises above the

UVLO_ON threshold, and the MP2884A waits

for EN to pull high. The PMBus is unavailable at

this stage.

t2~t3: at t2, EN pulls high, the data in the

EEPROM starts loading into the operating

registers. The entire EEPROM copy process

takes about 300µs, typically. During this stage,

the PMBus address is detected if the voltage on

ADDR is selected to set the PMBus address.

t3~t4: after the EEPROM copy is finished, if the

PMBus command OPERATION (01h) is pre-set

to an off state. The MP2884A halts at this stage

and waits for an OPERATION on command. If

OPERATION (01h) is pre-programmed to an on

state, the turn-on delay time (TON delay) begins

counting.

The

TON

delay

PMBus-

programmable from 0 to 3276.75ms with the

command TON_DELAY (60h).

t4~t5: when the TON delay time expires, the VID-

DAC starts ramping up VREF with a programmed

slew rate to the boot-up voltage. During soft

start, OCP_Total, OVP, and UVP are masked

until VREF reaches the target value.

In PWM-VID mode, before t5, PWM-VID should

remain at Hi-Z.

Figure 11b: MP2884A Power-On Sequence at Low-Power Mode

MP2884A Datasheet(PDF) 21 Page - Monolithic Power Systems

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