MP2884A datasheet(67/107 Pages) MPS

67 / 107 page

MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID

MP2884A Rev. 1.01

www.MonolithicPower.com

12/25/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

STATUS_CML (7Eh)

This register records the fault status of PMBus communication and EEPROM operation.

Command

STATUS_CML

Format

Unsigned binary

Bit

Access

Function

Bits

Bit Name

Description

INVALID_CMD

This bit is set when it receives an unsupported command code. This bit is in latch

mode. The CLEAR_FAULTS command can reset this bit.

INVALID_DATA

This bit is set when it receives invalid or unsupported data (host sends too many

bytes). This bit is in latch mode. The CLEAR_FAULTS command can reset this

bit.

PEC_FAULT

The PMBus interface supports the use of a packet error checking (PEC) byte that

is defined in the SMBus standard. The PEC byte is transmitted by the MP2884A

during a read transaction or sent by the bus host to the MP2884A during a write

transaction. If the PEC byte sent during a write transaction is incorrect, the

command is not executed, and this bit is set. This bit is in latch mode. The

CLEAR_FAULTS command can reset this bit.

CRC_FAULT

During the process of storing memory data to the EEPROM, the MP2884A

calculates the CRC for each bit and saves the final CRC code to the EEPROM.

During the process of restoring the EEPROM data to the memory, the MP2884A

calculates the CRC code with each bit. The MP2884A checks the CRC results

when the restore process is done. If the CRC result is incorrect, the VR does not

start up, and this bit is set. This bit is in latch mode. The CLEAR_FAULTS

command can reset this bit

MEMORY_PWD_

MATCH

There is write protection for the PMBus registers. If enabled, the PMBus registers

can be read only and are not writeable. The register MFR_USER_PWD (04h)

stores the password. Once the key is matched with MFR_USER_PWD, this bit is

set. Otherwise, this bit is reset. This bit is in live mode.

FAULT_STORE_FLAG

This device automatically records fault statuses to the EEPROM. Once the

power shuts down for any protection, the fault status record process is triggered,

and this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can

reset this bit.

CML_OTHER_FAULTS

If any of the below faults occur during PMBus communication, this bit is set.

Sending too few bits

2) Reading too few bits

Host sends or reads too few bytes

Reading too many bytes

This bit is in latch mode. The CLEAR_FAULTS command can reset this bit.

EEPROM_FAULTS

When restoring data from the EEPROM to the memory, this bit first checks the

signature register in address 00h of the EEPROM. If the signature is not

matched, this process is ceased immediately, and this bit is set. This bit is in

latch mode. The CLEAR_FAULTS command can reset this bit.

MP2884A Datasheet(PDF) 67 Page - Monolithic Power Systems

MP2884A Datasheet(HTML) 67 Page - Monolithic Power Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL