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MP2884A Datasheet(PDF) 59 Page - Monolithic Power Systems

No. de pieza MP2884A
Descripción Electrónicos  Digital, Multi-Phase PWM Controller with PMBus and PWM-VID
PDF  107 Pages
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Fabricante Electrónico  MPS [Monolithic Power Systems]
Página de inicio  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP2884A Datasheet(HTML) 59 Page - Monolithic Power Systems

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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MP2884A Rev. 1.01
www.MonolithicPower.com
59
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
MFR_DELAY_SET (5Dh)
The register sets the delay time of the power good signal and internal VOUT settle signal.
Command
MFR_ DELAY_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
x
x
SETTLE_DELAY
PG_DELAY
Bits
Bit Name
Description
15:13
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
12:9
SETTLE_DELAY
Delay time from when the output voltage reference reaches the target level to
when the internal VOUT settle signal becomes high. 100µs/LSB.
When VREF is ramping (soft start or DVID), the settle signal is low. When VREF is
settled, the settle signal is high. The DC loop or auto-power mode operate only
when the settle signal is high.
8:0
PG_DELAY
Delay time for asserting the power good signal. 1µs/LSB.
POWER_GOOD_ON (5Eh)
This register sets the output voltage threshold at which the power good signal is asserted.
Command
POWER_GOOD_ON
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
x
x
x
x
x
x
POWER_GOOD_ON
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
POWER_GOOD_ON
Output voltage threshold at which the power good signal is asserted.
6.25mV/LSB.
POWER_GOOD_OFF (5Fh)
This register sets the output voltage threshold at which the power good signal is deasserted.
Command
POWER_GOOD_OFF
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
x
x
x
x
x
x
POWER_GOOD_OFF
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
POWER_GOOD_OFF
Output voltage threshold at which the power good signal is deasserted.
6.25mV/LSB



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