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MP2884A Datasheet(PDF) 63 Page - Monolithic Power Systems |
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MP2884A Datasheet(HTML) 63 Page - Monolithic Power Systems |
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63 / 107 page ![]() MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID MP2884A Rev. 1.01 www.MonolithicPower.com 63 12/25/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. READ_CS9_10 (77h) This register is the phase-current ADC value of phase 9 and phase 10. An internal low-pass filter is used before ADC. Command READ_CS9_10 Format Unsigned binary Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r r r r r r r r r r r r r r r r Function x x Bits Bit Name Description 15:8 RESERVED Unused. X indicates that writes are ignored and reads are always 0. 7:0 RESERVED Unused. X indicates that writes are ignored and reads are always 0. Calculate the per-phase current sense with Equation (22): CSn = 256 x (ICS x Kcs x Rcs/1000 + 1.23) / 3.2 (22) Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS (in µA/A). If PHASE_CURRENT_RESOLUTION = 1 in register 44h, the CS report should be doubled. STATUS_BYTE (78h) This register returns one byte of information for critical faults. Command STATUS_BYTE Format Unsigned binary Bit 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w Function x x Bits Bit Name Description 7 RESERVED Unused. X indicates that writes are ignored and reads are always 0. 6 OFF This bit is asserted if the unit is not providing power to the output. This bit is in live mode. 5 VOUT_OV_FAULT Once output OVP occurs, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit. 4 IOUT_OC_FAULT Once output OCP occurs, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit. 3 VIN_UV_FAULT Once input UVP occurs, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit. 2 TEMPERATURE Once OTP or a warning occur, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit. 1 CML Once a communications, memory, or logic fault occurs, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit. 0 RESERVED Unused. X indicates that writes are ignored and reads are always 0. |
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