MP2884A datasheet(64/107 Pages) MPS

64 / 107 page

MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID

MP2884A Rev. 1.01

www.MonolithicPower.com

12/25/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

STATUS_WORD (79h)

This register returns two bytes of information for fault statuses. Based on this information, the host can

get more information by reading the appropriate status registers. The low byte of STATUS_WORD is

the same as the STATUS_BYTE register.

Command

STATUS_WORD

Format

Unsigned binary

Bit

Access

Function

Bits

Bit Name

Description

VOUT

Once output OVP, UVP, or a warning occurs, this bit is set. This bit is in latch

mode. The CLEAR_FAULTS command can reset this bit.

IOUT/POUT

Once output OCP, over-power protection (OPP), or a warning occurs, this bit is

set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit.

INPUT

Once any protection or warning of the input voltage, input current, or input power

occurs, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command

can reset this bit.

READ_DATA_RDY

When READ_PIN, READ_POUT, or READ_EFFECIENCY uses average window

mode and once the average window calculation is done, the data is ready in the

resistor, and this bit is set. Sending the command START_CATCH_AVE triggers

a new averaging process and resets this bit.

POWER_GOOD

When VOUT rises higher than the POWER_GOOD_ON level during the soft-start

process and the delay time is reached, this bit is asserted. This bit is in live

mode.

10:9

RESERVED

Unused. X indicates that writes are ignored and reads are always 0.

WATCH_DOG_OVF

The monitor value calculation has a watchdog timer. If the timer expires, the

monitor value calculation state machine and the timer are reset. Meanwhile, this

bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this

bit

RESERVED

Unused. X indicates that writes are ignored and reads are always 0.

OFF

This bit is asserted if the unit is not providing power to the output. This bit is in

live mode.

VOUT_OV_FAULT

Once output OVP occurs, this bit is set. This bit is in latch mode. The

CLEAR_FAULTS command can reset this bit.

IOUT_OC_FAULT

Once output OCP occurs, this bit is set. This bit is in latch mode. The

CLEAR_FAULTS command can reset this bit.

VIN_UV_FAULT

Once input UVP occurs, this bit is set. This bit is in latch mode. The

CLEAR_FAULTS command can reset this bit.

TEMPERATURE

Once OTP or a warning occurs, this bit is set. This bit is in latch mode. The

CLEAR_FAULTS command can reset this bit.

CML

Once a communication, memory, or logic fault occurs, this bit is set. This bit is in

latch mode. The CLEAR_FAULTS command can reset this bit.

RESERVED

Unused. X indicates that writes are ignored and reads are always 0.

MP2884A Datasheet(PDF) 64 Page - Monolithic Power Systems

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