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MP2884A Datasheet(PDF) 46 Page - Monolithic Power Systems |
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MP2884A Datasheet(HTML) 46 Page - Monolithic Power Systems |
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46 / 107 page ![]() MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID MP2884A Rev. 1.01 www.MonolithicPower.com 46 12/25/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 5 PHASE_CNT_HOLD_ CB_EN Enable bit for holding the CB loop for a certain amount of time when the phase count changes. 0: disable 1: enable 4 DVID_HOLD_CB_EN Enable bit for holding the CB loop for a certain amount of time during DVID. 0: disable 1: enable 3:0 CB_LOOP_HOLD_TIME Current balance loop holding time. 100µs/LSB. MFR_FS_LOOP_CTRL (32h) This register is used for PWM frequency loop setting. Command MFR_FS_LOOP_CTRL Format Unsigned binary Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Function x FS_LOOP_HOLD_TIME FS_LOOP_KI Bits Bit Name Description 15 RESERVED Unused. X indicates that writes are ignored and always read as 0. 14 VFB_HOLD_FS_EN Enable bit for holding the frequency loop for a certain amount of time when VFB exceeds the VO_REF - 25mV or VO_REF + 20mV threshold. 0: disable 1: enable 13 PHASE_CNT_HOLD_FS _EN Enable bit for holding the frequency loop for a certain amount of time when the phase count changes. 0: disable 1: enable 12 DVID_HOLD_FS_EN Enable bit for holding the frequency loop for a certain amount of time during DVID. 0: disable 1: enable 11:8 FS_LOOP_HOLD_TIME Frequency loop holding time. 100µs/LSB. 7 FS_LOOP_EN Enable bit for the PWM frequency loop. 0: disable 1: enable 6:0 FS_LOOP_KI PWM frequency loop integral parameter. MFR_T_ALERT_CTRL (34h) This register sets the thermal alert pin (TALERT#) behavior. Command MFR_T_ALERT_CTRL Format Unsigned binary Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Function x x T_ALT_DELAY TSNS_T_ALT_THRE |
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